; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
;
TITLE * * * * AM29116.DEF FILE - D. E. WHITE - JANUARY 12, 1982 * * *
;
;
;
;
; This file was created as a master file from which the user can create
; a .DEF file for a particular application.  Documentation on the Am29116
; instruction set can be found in the data sheet and in "The Am29116", 
; a CUSTOMER EDUCATION CENTER publication, revised to include this file
; and its companion, CONTROLR.SRC, a test file.
;
;
; The file DISKCTLR.DEF was created by editing this file; DISKCTLR.SRC
; provides an example of disk controller microroutines.
;
; This file was created for use in AMD CUSTOMER EDUCATION CENTER seminars.
;
; Advanced Micro Devices reserves the right to make changes in its product
; without notice in order to improve design or performance characteristics.
; The company assumes no responsibility for the use of any circuits or     
; programs described herein.
; 
; Am29116 Mnemonics Copyright  c  1982 Advanced Micro Devices, Inc.
EJECT
;   
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
WORD   64		; ASSUMED LAYOUT - CHANGE AS NEEDED
;
; This file contains the EQUs and DEFs for a "typical" Am29116 controller
;
; CREATED APRIL 21, 1981
; UPDATED JAN 12, 1982 DEW
;     
; INDEX:
;			BYTE-WORD MODE SELECT [M]
;		        NUMBER [N]
;			RAM REGISTERS [R]
; Parts included are:    Am2910 (SUB STATEMENT)  
; 			 Am29116 - ALL VALID COMBINATIONS
;			 Am2914
;			 Am2940	
;			 Am2942
;			 Am2904 - PARTIAL ONLY! (2**22 POSSIBLE VARIATIONS)
;			 Am2925 - CYCLE SELECT, OTHER CONTROLS DRAFTED ONLY
;			 Am2950
;
;	INDEX TO Am29116 INSTRUCTIONS - [i] REFERS TO ALLOWED MNEMONICS GROUP 
;
;		SINGLE OPERAND [1], [2], [3], [4]
;		TWO OPERAND    [5], [6], [7], [8]
;		SHIFT	       [9], [10], [11]
;		ROTATE	       [12], [13], [14]
;		BIT-ORIENTED   [15], [16], [17]
;		ROTATE & MERGE [18]
;		ROTATE & COMPR [19]
;		PRIORITIZE     [20], [21], [22], [23], [24], [25]
;		CYCLIC REDUNDANCY CHECKS
;		NOOP
;		STATUS	       [26], [27]
;		TEST STATUS    [CT]
;
EJECT
; *************************************************
; GENERAL MNEMONICS 
; *************************************************
;
; ****************************
; BYTE - WORD MODE SELECT [M]
; ****************************
;
B:		EQU		1B#0	; BYTE MODE
W:		EQU		1B#1	; WORD MODE
;
; *************************************************
; N SELECT [N]		constant for Am29116
; *************************************************
;
N0:		EQU		H#0	; 0
N1:		EQU		H#1	;
N2:		EQU		H#2	;
N3:		EQU		H#3	;
N4:		EQU		H#4	;
N5:		EQU		H#5	;
N6:		EQU		H#6	;
N7:		EQU		H#7	;
N8:		EQU		H#8	;
N9:		EQU		H#9	;
NA:		EQU		H#A	;
NB:		EQU		H#B	;
NC:		EQU		H#C	;
ND:		EQU		H#D	;
NE:		EQU		H#E	;
NF:		EQU		H#F	;
EJECT
;
; ***************************************************
; 32 RAM REGISTERS [R]
; ***************************************************
;
R0:		EQU		5D#0	; 00000
R1:		EQU		5D#1	;
R2:		EQU		5D#2	;
R3:		EQU		5D#3	;
R4:		EQU		5D#4	;
R5:		EQU		5D#5	;
R6:		EQU		5D#6	;
R7:		EQU		5D#7	;
R8:		EQU		5D#8	;
R9:		EQU		5D#9	;
R10:		EQU		5D#10	;
R11:		EQU		5D#11	;
R12:		EQU		5D#12	;
R13:		EQU		5D#13	;
R14:		EQU		5D#14	;
R15:		EQU		5D#15	;
R16:		EQU		5D#16	;
R17:		EQU		5D#17	;
R18:		EQU		5D#18	;
R19:		EQU		5D#19	;
R20:		EQU		5D#20	;
R21:		EQU		5D#21	;
R22:		EQU		5D#22	;
R23:		EQU		5D#23	;
R24:		EQU		5D#24	;
R25:		EQU		5D#25	;
R26:		EQU		5D#26	;
R27:		EQU		5D#27	;
R28:		EQU		5D#28	;
R29:		EQU		5D#29	;
R30:		EQU		5D#30	;
R31:		EQU		5D#31	;
EJECT
; *************************
; Am2910 INSTRUCTION SET     
; Microprogram Controller
; ************************
;
JZ:	EQU	H#0 	; JUMP ZERO - RESET
CJS:	EQU	H#1	; COND JUMP SUBROUTINE - PIPELINE
JMAP:	EQU	H#2	; JUMP MAP (DECODE)
CJP:	EQU	H#3	; COND JUMP PIPELINE
PUSH:	EQU	H#4	; PUSH, COND LOAD CNTR & CONTINUE
JSRP:	EQU	H#5	; COND JUMP SUBROUTINE - REGISTER OR PIPELINE
CJV:	EQU	H#6 	; COND JUMP VECTOR MAP
JRP:	EQU	H#7	; COND JUMP REGISTER OR PIPELINE
RFCT:	EQU	H#8	; REPEAT LOOP, ADDR ON STACK, COUNT DOWN COUNTER
RPCT:	EQU	H#9	; REPEAT LOOP, ADDR IN PIPELINE, COUNT DOWN COUNTER
CRTN:	EQU	H#A	; COND RETURN FROM SUBROUTINE
CJPP:	EQU	H#B	; COND JUMP PIPELINE AND POP STACK
LDCT:	EQU	H#C	; LOAD COUNTER AND CONTINUE
LOOP:	EQU  	H#D	; REPEAT LOOP UNTIL TEST TRUE; ADDR ON STACK
CONT:	EQU	H#E	; CONTINUE
TWB:	EQU	H#F	; DEAD-MAN TIMER, REPEAT LOOP, ADDR ON STACK, FAIL
;			  ADDR IN PIPELINE, COUNT-DOWN COUNTER (3-WAY)
;
; ************************************************************************
AM2910: SUB	4VH#E,3VX,12V%X    ; AM2910-COND MUX-BRANCH/COUNTER FIELDS
; ************************************************************************
;
; THE AM2910 FIELDS ARE GROUPED AS A SUB STATEMENT WHICH APPEARS IN ALL Am29116
; DEF STATEMENTS.  THE ACTUAL FIELDS REQUIRED CAN BE ALTERED AS NEEDED 
;
;
EJECT
; * * * * * * * * * * * * * * * * *
; Am29116 CONTROL LINES
; 16-Bit Bipolar Microprocessor
; * * * * * * * * * * * * * * * * * 
;
OEYEN:	 	EQU		B#0	; Y BUS ENABLE
OEYDIS:		EQU		B#1
;
DLE.EN:		EQU		B#1	; DATA LATCH ENABLE
DLE.DIS:	EQU		B#0
;
OETEN:		EQU		B#1	; T BUS ENABLE
OETDIS:		EQU		B#0
;
SRE.EN:		EQU		B#0	; STATUS REGISTER ENABLE
SRE.DIS:	EQU		B#1
;
IEN:		EQU		B#0	; INSTRUCTION ENABLE
IDIS:		EQU		B#1
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
ZZZZZ:	SUB	1VB#0, 1VB#1, 1VB#0, 1VB#0, 1VB#0, 24X
;
;               OEYEN  DLE.EN OETDIS SRE.EN IEN    MISC
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
;
; THE "SLEEPER" CONTAINS THE Am29116 CONTROL LINES AND 24 DON'T CARE POSITIONS
; WHICH THE USER CAN DEFINE TO BE WHATEVER NEEDED TO COMPLETE THE MICROWORD
; THE "SLEEPER" APPEARS IN ALL Am29116 INSTRUCTION DEF STATEMENTS     
;                
EJECT
; *****************************
; SINGLE OPERAND INSTRUCTIONS
; *****************************
;
; OPCODES [1]
;
MOVE:		EQU		H#C	; 1100 MOVE
COMP:		EQU		H#D	; 1101 COMP
INC:		EQU		H#E	; 1110 INC     INCREMENT
NEG:		EQU		H#F	; 1111 NEG     INCREMENT COMP
;
; SOURCE-DESTINATION SELECT [2]
;
SORA:		EQU		H#0	; RAM	ACC
SORY:		EQU		H#2	; RAM	Y BUS
SORS:		EQU		H#3	; RAM	STATUS
SOAR:		EQU		H#4	; ACC	RAM
SODR:		EQU		H#6	; D	RAM
SOIR:		EQU		H#7	; I	RAM
SOZR:		EQU		H#8	; 0	RAM
SOZER:		EQU		H#9	; D(0E) RAM
SOSER:		EQU		H#A	; D(SE) RAM
SORR:		EQU		H#B	; RAM	RAM
;
; ************************************************************
SOR: DEF AM2910,1V,  B#10,4V,    4V,         5V%, ZZZZZ;SINGLE OPERAND RAM
;
;		MODE,QUAD,OPCODE,SOURCE-DEST,REGISTER
;		[M]	    [1]	     [2]        [R]
; ************************************************************
;     
; SOURCE (R/S) [3]
;
SOA:		EQU		H#4	; ACC
SOD:		EQU		H#6	; D
SOI:		EQU		H#7	; I
SOZ:		EQU		H#8	; 0
SOZE:		EQU		H#9	; D(0E)
SOSE:		EQU		H#A	; D(SE)
;
; DESTINATION [4]
;
NRY:		EQU		D#0	; Y BUS
NRA:		EQU		D#1	; ACC
NRS:		EQU		D#4	; STATUS
NRAS:		EQU		D#5	; ACC,STATUS
;
; ***************************************************************
SONR: DEF AM2910,1V,  B#11,4V,    4V,    5V%, ZZZZZ ; SINGLE OPERAND NON-RAM
;
;		MODE,QUAD,OPCODE,SOURCE,DESTINATION
;		[M]	    [1]    [3]      [4]
; ***************************************************************
EJECT
; ***********************************
; TWO OPERAND INSTRUCTIONS
; ***********************************
;
; OPCODES [5]
;
SUBR:		EQU		H#0	; S minus R
SUBRC:		EQU		H#1	; S minus R with carry
SUBS:		EQU		H#2	; R minus S
SUBSC:		EQU		H#3	; R minus S with carry
ADD:		EQU		H#4	; R plus S
ADDC:		EQU		H#5	; R plus S with carry
AND:		EQU		H#6	; R . S
NAND:		EQU		H#7	; R . S
EXOR:		EQU		H#8	; R   S
NOR:		EQU		H#9	; R + S
OR:		EQU		H#A	; R + S
EXNOR:		EQU		H#B	; R   S
;
;
; SOURCE-DESTINATION [6]		; R	S	DEST
;
TORAA:		EQU		H#0	; RAM	ACC	ACC
TORIA:		EQU		H#2	; RAM	I	ACC
TODRA:		EQU		H#3	; D	RAM	ACC
TORAY:		EQU		H#8	; RAM	ACC	Y BUS
TORIY:		EQU		H#A	; RAM	I	Y BUS
TODRY:		EQU		H#B	; D	RAM	Y BUS
TORAR:		EQU		H#C	; RAM	ACC	RAM
TORIR:		EQU		H#E	; RAM	I	RAM
TODRR:		EQU		H#F	; D	RAM	RAM
;
; ************************************************************
TOR1: DEF AM2910,1V,  B#00,4V,         4V,    5V%, ZZZZZ ; TWO OPERAND RAM (1)
;
;		MODE,QUAD,SOURCE-DEST,OPCODE,REGISTER
;		[M]             [6]     [5]     [R]
; ************************************************************
;
; THE [i] IN THE COMMENT BELOW THE VARIABLE-FIELD REFERS TO THE ALLOWED 
; MNEMONIC GROUP.  EXAMPLE: MODE REFERS VIA [M] TO THE BYTE-WORD SELECT.
; EXAMPLE: THE ALLOWED OPCODE SUBSTITUTIONS IN TOR1 COME FROM GROUP [5]
; WHILE THE ALLOWED SOURCE-DESTINATIONS COME FROM GROUP [6].
;
EJECT
;
;
;
;
;
; SOURCE-DESTINATION [7]                      R     S       DEST
;
TODAR:		EQU		H#1	; D	ACC	RAM
TOAIR:		EQU		H#2	; ACC	I	RAM
TODIR:		EQU		H#5	; D	I	RAM
;
; ************************************************************
TOR2: DEF AM2910,1V,  B#10,4V,         4V,    5V%, ZZZZZ ; TWO OPERAND RAM (2)
;
;		MODE,QUAD,SOURCE-DEST,OPCODE,REGISTER
;		[M]           [7]       [5]    [R]
; ************************************************************
;
; SOURCE [8]                              R     S
;
TODA:		EQU		H#1	; D	ACC
TOAI:		EQU		H#2	; ACC	I
TODI:		EQU		H#5	; D	I
; ***********************************************************
TONR: DEF AM2910,1V,   B#11,4V,    4V,    5V%, ZZZZZ ; TWO OPERAND NON-RAM
;
;		MODE, QUAD,SOURCE,OPCODE,DESTINATION
;		[M]	     [8]    [5]     [4]
; ***********************************************************
EJECT
; **************************************************
; SHIFT INSTRUCTIONS
; **************************************************
;
; DIRECTION AND INPUT [9]
;
SHUPZ:		EQU		H#0	; UP 0
SHUP1:		EQU		H#1	; UP 1
SHUPL:		EQU		H#2	; UP QLINK
SHDNZ:		EQU		H#4	; DOWN 0
SHDN1:		EQU		H#5	; DOWN 1
SHDNL:		EQU		H#6	; DOWN QLINK
SHDNC:		EQU		H#7	; DOWN QC
SHDNOV:		EQU		H#8	; DOWN QN QOVR
;
;
; SOURCE [10] 
;
SHRR:		EQU		H#6	; RAM	RAM
SHDR:		EQU		H#7	; D	RAM
;
;
; *****************************************************
SHFTR: DEF AM2910,1V,  B#10,4V,         4V,    5V%, ZZZZZ ; SHIFT RAM
;
;		MODE,QUAD,SOURCE,DIRECT-INPT,REGISTER
;		[M]        [10]       [9]     [R]
; *****************************************************
;    
;
; SOURCE [11]
;
SHA:		EQU		H#6	; ACC
SHD:		EQU		H#7	; D
;
;
; *****************************************************
SHFTNR: DEF AM2910,1V,  B#11,4V,    4V,    5V%, ZZZZZ ; SHIFT NON-RAM
;
;		MODE,QUAD,SOURCE,DIRECT-INP,DESTINATION
;		[M]	    [11]   [9]        [4](NRY; NRA ONLY)
; *****************************************************
;
EJECT
; **************************************************
;ROTATE INSTRUCTIONS
; **************************************************
;
; SOURCE-DESTINATION [12]
;
RTRA:		EQU		H#C	; RAM	ACC
RTRY:		EQU		H#E	; RAM	Y BUS
RTRR:		EQU		H#F	; RAM	RAM
;
;
; *****************************************************
ROTR1: DEF  AM2910,1V,  B#00,4V,4V,        5V%, ZZZZZ ; ROTATE RAM (1)
;
;		MODE,QUAD,N,SOURCE-DEST,REGISTER
;		[M]      [N]     [12]     [R]
; *****************************************************
;
; SOURCE-DESTINATION [13]
; 
RTAR:		EQU		H#0	; ACC	RAM
RTDR:		EQU		H#1	; D	RAM
;
;
; *****************************************************
ROTR2: DEF  AM2910,1V,  B#01,4V,4V,        5V%, ZZZZZ ; ROTATE RAM (2)
;
;		MODE,QUAD,N,SOURCE-DEST,REGISTER
;		[M]      [N]    [13]      [R]
; *****************************************************
;    
; SOURCE DESTINATION [14]
;
RTDY:		EQU		D#24	; D	Y BUS
RTDA:		EQU		D#25	; D	ACC
RTAY:		EQU		D#28	; ACC	Y BUS
RTAA:		EQU		D#29	; ACC	ACC
;
;
; *****************************************************
ROTNR: DEF  AM2910,1V,  B#11,4V,H#C,      5V%, ZZZZZ ; ROTATE NON-RAM
;
;		MODE,QUAD,N,FIXED CODE,DESTINATION
;		[M]      [N]               [14]
; *****************************************************
EJECT
; ***************************************************
; BIT ORIENTED INSTRUCTIONS
; ***************************************************
;
; OPCODES [15]
;
SETNR:		EQU		H#D	; SET RAM, BIT N
RSTNR:		EQU		H#E	; RESET RAM, BIT N
TSTNR:		EQU		H#F	; TEST RAM, BIT N
;
;
; ********************************************************
BOR1: DEF AM2910,1V,  B#11,4V,4V,   5V%, ZZZZZ ; BIT ORIENTED RAM (1)
;
;		MODE,QUAD,N,OPCODE,REGISTER
;		[M]      [N]  [15]    [R]
; ********************************************************
;
;
; OPCODES [16]
;
LD2NR:		EQU		H#C	; 2^N --- RAM
LDC2NR:		EQU		H#D	; 2^N --- RAM
A2NR:		EQU		H#E	; RAM + 2^N - RAM
S2NR:		EQU		H#F	; RAM - 2^N - RAM
;
;
; ********************************************************
BOR2: DEF AM2910,1V,  B#10,4V,4V,   5V%, ZZZZZ ; BIT ORIENTED RAM (2)
;
;		MODE,QUAD,N,OPCODE,REGISTER
;		[M]      [N]  [16]    [R]
; ********************************************************
EJECT
;
;
;
;
;
; OPCODES [17]
;
TSTNA:		EQU		D#0	; TEST ACC, BIT N
RSTNA:		EQU		D#1	; RESET ACC, BIT N
SETNA:		EQU		D#2	; SET ACC, BIT N
A2NA:		EQU		D#4	; ACC + 2^N -- ACC
S2NA:		EQU		D#5	; ACC - 2^N --ACC
LD2NA:		EQU		H#6	; 2^N -- ACC
LDC2NA:		EQU		D#7	; 2^N -- ACC
TSTND:		EQU		D#16	; TEST D, BIT N
RSTND:		EQU		D#17	; RESET D, BIT N
SETND:		EQU		D#18	; SET D, BIT N
A2NDY:		EQU		D#20	; D + 2^N -- Y BUS
S2NDY:		EQU		D#21	; D - 2^N -- Y BUS
LD2NY:		EQU		D#22	; 2^N -- Y BUS
LDC2NY:		EQU		D#23	; 2^N -- Y BUS
;
;
; *********************************************************
BONR: DEF AM2910,1V,  B#11,4V,B#110,    5V%, ZZZZZ ; BIT ORIENTED NON-RAM
;
;		MODE,QUAD,N,FIXED CODE,OPCODE
;		[M]      [N]            [17]
; *********************************************************
EJECT
; **************************************************
; ROTATE AND MERGE
; **************************************************
;
; SOURCE-DEST SELECT [U,S,MASK-DEST] [18]
;
;					  ROT   NON-ROT  MASK-DEST
MDAI:		EQU		H#7	; D	ACC	I
MDAR:		EQU		H#8	; D 	ACC	RAM
MDRI:		EQU		H#9	; D	RAM	I
MDRA:		EQU		H#A	; D	RAM	ACC
MARI:		EQU		H#C	; ACC	RAM	I
MRAI:		EQU		H#E	; RAM	ACC	I
;
;
; **********************************************************
ROTM: DEF AM2910,1V,  B#01,4V,4V,        5V%, ZZZZZ ;ROTATE AND MERGE
;
;		MODE,QUAD,N,SOURCE-DEST,REGISTER
;		[M]      [N]    [18]       [R]
; **********************************************************
;     
;
;
;
;
; **************************************************
; ROTATE AND COMPARE
; **************************************************
;
; ROT.SRC(U)-NON ROT.SRC(S)/DEST-MASK(S)[19]
;
CDAI:		EQU		H#2	; D	ACC	I
CDRI:		EQU		H#3	; D	RAM	I
CDRA:		EQU		H#4	; D	RAM	ACC
CRAI:		EQU		H#5	; RAM	ACC	I
;
;
; ********************************************
ROTC: DEF AM2910,1V,  B#01,4V,4V,             5V%, ZZZZZ ; ROTATE AND COMPARE
;
;		MODE,QUAD,N,SOURCE-DEST-MASK,REGISTER
;		[M]      [N]       [19]        [R]
; *********************************************
EJECT
;
; **************************************************
; PRIORITIZE
; **************************************************
;
; SOURCE [20]
;
PRT1A:		EQU		H#7	; ACC
PR1D:		EQU		H#9	; D
;
;
; DESTINATION [21]
;
PR1A:		EQU		H#8	; ACC
PR1Y:		EQU		H#A	; Y BUS
PR1R:		EQU		H#B	; RAM
;
; ***********************************************
PRT1: DEF AM2910,1V,  B#10,4V,	      4V,    5V%, ZZZZZ ; RAM ADDR MASK(S)
;
; 		MODE,QUAD,DESTINATION,SOURCE,REG-MASK
;		[M]	      [21]     [20]    [R]
; ***********************************************
;    
;
; DESTINATION [23]
;
PR2A:		EQU		H#0	; ACC
PR2Y:		EQU		H#2	; Y BUS
;
; MASK (S) [22]
;
PRA:		EQU		H#8	; ACC
PRZ:		EQU		H#A	; 0
PRI:		EQU		H#B	; I
;
;
; ***********************************************
PRT2: DEF AM2910,1V,  B#10,4V,  4V,  5V%, ZZZZZ ; PRIORITIZE RAM
;
;		MODE,QUAD,MASK,DEST,REG-SOURCE
;		[M]       [22] [23]    [R]
; ***********************************************
EJECT
;
;
;
;
; SOURCE (R) [24]
;
PR3R:		EQU		H#3	; RAM
PR3A:		EQU		H#4	; ACC
PR3D:		EQU		H#6	; D
;
;
; ***********************************************
PRT3: DEF AM2910,1V,  B#10,4V,  4V,    5V%, ZZZZZ ; PRIORITIZE RAM
;
;		MODE,QUAD,MASK,SOURCE,REG-DEST
;		[M]       [22]  [24]    [R]
; ***********************************************
;     
;
; SOURCE (R) [25]
;
PRTA:		EQU		H#4	; ACC
PRTD:		EQU		H#6	; D
;
;
; **********************************************
PRTNR: DEF  AM2910,1V,  B#11,4V,  4V,    5V%, ZZZZZ ; PRIORITIZE NON-RAM
;
;		   MODE,QUAD,MASK,SOURCE,DESTINATION
;		   [M]       [22]  [25]    [4](NRY,NRA ONLY)
; **********************************************
EJECT
;
;
;
;
;
; **********************************************
; CYCLIC REDUNDANCY CHECK
; **********************************************
;
;
; *******************************************
CRCF: DEF AM2910,B#11001100011,5V%, ZZZZZ ; FORWARD
; *******************************************
;
;
; *******************************************
CRCR: DEF AM2910,B#11001101001,5V%, ZZZZZ ; REVERSE
; *******************************************
;
;
;
;
;     
; ********************************************
;
; NOOP
;
; ********************************************
NOOP: DEF AM2910,H#7140, ZZZZZ			; NO OPERATION
; ********************************************
;
EJECT
; ************************************************
; STATUS
; ************************************************
;
; OPCODE [26]
;
SONZC:		EQU		5D#3	; SET OVR,N,C,Z
SL:		EQU		5D#5	; SET LINK
SF1:		EQU		5D#6	; SET FLAG 1
SF2:		EQU		5D#9	; SET FLAG 2
SF3:		EQU		5D#10	; SET FLAG 3
;
;
; **************************************************
SETST: DEF AM2910,B#011,H#BA,5V%, ZZZZZ ; SET STATUS
;
;			   OPCODE
;			    [26]
; **************************************************
;    
;
;
; OPCODE [27]
;
RONCZ:		EQU		D#3	; RESET OVR,N,C,Z
RL:		EQU		D#5	; RESET LINK
RF1:		EQU		D#6	; RESET FLAG 1
RF2:		EQU		D#9	; RESET FLAG 2
RF3:		EQU		D#10	; RESET FLAG 3
;
;*****************************************************
RSTST: DEF AM2910,B#011,H#AA,5V%, ZZZZZ	; RESET STATUS
;
;			    OPCODE
;			    [27]
; ****************************************************
EJECT
;
;
; ****************************************************
SVSTR: DEF  AM2910,1V,  B#10,H#7A, 5V%,     ZZZZZ ; SAVE STATUS-RAM
;
;		   MODE,QUAD,FIXED,RAM ADDRESS/DEST
;		    [M]			[R]
; ****************************************************
;
;
;*****************************************************
SVSTNR: DEF  AM2910,1V, B#11,H#7A, 5V%,       ZZZZZ ; SAVE STATUS NON-RAM
;
;		   MODE,QUAD,FIXED,DESTINATION
;		   [M]		  [4](NRY,NRA ONLY)
; ****************************************************
;
;      
; *************************************************
; TEST STATUS
; *************************************************
;
; OPCODE (CT)
;
TNOZ:		EQU		D#0	; TEST (N OVR) + Z
TNO:		EQU		D#2	; TEST N OVR
TZ:		EQU		D#4	; TEST Z
TOVR:		EQU		D#6	; TEST OVR
TLOW:		EQU		D#8	; TEST LOW
TC:		EQU		D#10	; TEST C
TZC:		EQU		D#12	; TEST Z + C
TN:		EQU		D#14	; TEST N
TL:		EQU		D#16	; TEST LINK
TF1:		EQU		D#18	; TEST FLAG 1
TF2:		EQU		D#20	; TEST FLAG 2
TF3:		EQU		D#22	; TEST FLAG 3
;
;
; *****************************************************
TEST: DEF AM2910,B#011,H#9A,5V%, ZZZZZ ;  TEST STATUS
;
;		 FIXED,     OPCODE
;			    [CT]
; *****************************************************
EJECT
; * * * * * * * * * * * * * * * * 
;
; Am2914 INSTRUCTION SET
; Vectored Priority Interrupt Controller
;   
; * * * * * * * * * * * * * * * *
;
MCLR:	EQU	H#0	; MASTER CLEAR
CLRIN:	EQU	H#1	; CLEAR ALL INTERRUPTS
CLRMB:	EQU	H#2	; CLEAR INTERRUPTS FROM M-BUS
CLRMR:	EQU	H#3	; CLEAR INTERRUPTS FROM MASK REGISTER
CLRVC:	EQU	H#4	; CLEAR INTERRUPT FROM LAST VECTOR READ
RDVC:	EQU	H#5	; READ VECTOR
RDSTA:	EQU	H#6	; READ STATUS REGISTER
RDM:	EQU	H#7	; READ MASK REGISTER
SETM:	EQU	H#8	; SET MASK REGISTER
LDSTA:	EQU	H#9	; LOAD STATUS REGISTER
BCLRM:	EQU	H#A	; BIT CLEAR MASK REGISTER
BSETM:	EQU	H#B	; BIT SET MASK REGISTER
CLRM:	EQU	H#C	; CLEAR MASK REGISTER
DISIN:	EQU	H#D	; DISABLE INTERRUPT REQUEST
LDM:	EQU	H#E	; LOAD MASK REGISTER
ENIN:	EQU	H#F	; ENABLE INTERRUPT REQUEST
;
EJECT
; * * * * * * * * * * * * * * * * * * * 
;
; Am2940 DMA CONTROL UNIT
; DMA Address Generator
; TO USE - DELETE THE .40 AND DELETE THE Am2942 INSTRUCTION SET
; DUE TO DUPLICATE MNEMONICS
;
; * * * * * * * * * * * * * * * * * * * 
; INSTRUCTIONS
;
WRCR.40:	EQU	Q#0	; WRITE CONTROL REGISTER
RDCR.40:	EQU	Q#1	; READ CONTROL REGISTER
RDWC.40:	EQU	Q#2	; READ WORD COUNTER
RDAC.40:	EQU	Q#3	; READ ADDRESS COUNTER
REIN.40:	EQU	Q#4	; REINITIALIZE COUNTERS
LDAD.40:	EQU	Q#5	; LOAD ADDRESS
LDWC.40:	EQU	Q#6	; LOAD WORD COUNT
ENCT.40:	EQU	Q#7	; ENABLE COUNTERS
;
;CONTROL MODE BYTE
;NOTE - BITS 3 THROUGH 7 ARE DON'T CARE
;
WC1I.40:	EQU	8Q#0%	; WORD COUNT EQUALS ONE, INCREMENT ADDR CNTR
WCCI.40:	EQU	8Q#1%	; WORD COUNT COMPARE, INCREMENT ADDR CNTR
ADCI.40:	EQU	8Q#2%	; ADDR COMPARE, INCREMENT ADDR CNTR
WCOI.40:	EQU	8Q#3%	; WORD CNTR CARRY OUT, INCREMENT ADDR CNTR
WC1D.40:	EQU	8Q#4%	; WORD COUNT EQUALS ONE, DECREMENT ADDR CNTR
WCCD.40:	EQU	8Q#5%	; WORD COUNT COMPARE, DECREMENT ADDR CNTR
ADCD.40:	EQU	8Q#6%	; ADDR COMPARE, DECREMENT ADDR CNTR
WCOD.40:	EQU	8Q#7%	; WORD CNTR CARRY OUT, DECREMENT ADDR CNTR
EJECT
; **********************************
; Am2942 INSTRUCTION SET
; Programmable Timer/Counter
; DMA Address Generator 
; *********************************
;
; DMA INSTRUCTIONS - ALSO REQUIRES INSTRUCTION ENABLE = LOW
;
WRCR:		EQU	H#0	; WRITE CONTROL REGISTER
RDCR:		EQU	H#1	; READ CONTROL REGISTER
RDWC:		EQU	H#2	; READ WORD COUNTER
RDAC:		EQU	H#3	; READ ADDRESS COUNTER
REIN:		EQU	H#4	; REINITIALIZE COUNTERS
LDAD:		EQU	H#5	; LOAD ADDRESS
LDWC:		EQU	H#6	; LOAD WORD COUNT
ENCT:		EQU	H#7	; ENABLE COUNTERS
;
; DMA INSTRUCTION - INSTRUCTION ENABLE = HIGH
;
; ALL OF THE ABOVE BECOME INSTRUCTION DISABLE
;
; TIMER/COUNTER INSTRUCTIONS - INSTRUCTION ENABLE = LOW
;
WCRT:		EQU	H#8 	; WRITE CONTROL REGISTER, T/C
REAC:		EQU	H#9	; REINITIALIZE ADDRESS COUNTER
RWCT:		EQU	H#A	; READ WORD COUNTER, T/C
RACT:		EQU	H#B	; READ ADDRESS COUNTER, T/C
RAWC:		EQU	H#C	; REINITIALIZE ADDRESS AND WORD COUNTERS
LDAT:		EQU	H#D	; LOAD ADDRESS, T/C
LWCT:		EQU	H#E	; LOAD WORD COUNT, T/C
REWC:		EQU	H#F	; REINITIALIZE WORD COUNTER
;
; TIMER/COUNTER INSTRUCTIONS - INSTRUCTION ENABLE = HIGH
;
; ALL OF THE ABOVE T/C INSTRUCTIONS BECOME INSTRUCTION DISABLE, T/C
;
EJECT
; **************************************************************************
;
; Am2904 INSTRUCTION SET - PARTIAL ONLY!!!!!    
;  BUILD ONLY WHAT YOU NEED!!!
; Status and Shift Control Unit
;   
; * * * * * * * * * * * * * * * * * * * * * * * * * *
;
;
; DOWN SHIFTING
;
SDZRZQ:		EQU	H#0		; Z->RN; Z->QN
SDOROQ:		EQU	H#1		; 1->RN; 1->QN
SLN.RECOVER:    EQU	H#2		; 0->RN; R0->Mc; MN->QN
DDOR:		EQU	H#3		; 1->RN; R0->QN
DDMCR:		EQU	H#4		; Mc->RN; R0->QN
DLN.RECOVER:	EQU	H#5		; MN->RN; R0->QN
DDZR:		EQU	H#6		; 0->RN; R0->QN
DDZRQMC:	EQU	H#7		; 0->RN; R0->QN; Q0->Mc
SDROTMC:	EQU	H#8		; ROT.R; R0->Mc; ROT.Q
SDROTC:		EQU	H#9		; ROT.R WITH Mc; ROT.Q
SDROT:		EQU	H#A		; ROT.R; ROT.Q
SDIC:		EQU	H#B		; Ic->RN; R0->QN
DDROTC:		EQU	H#C		; Mc->RN; R0->QN; Q0->Mc
DDROTMC:	EQU	H#D		; Q0->RN; R0->QN; Q0->Mc
DDINIOVR:	EQU	H#E		; IN EXOR IOVR -> RN; R0->QN
DDROT:		EQU	H#F		; DOUBLE PRECISION ROTATE DOWN
;
;
; UP SHIFTING (INCOMPLETE)
;
SURZQZ:		EQU	H#2		; R0<-0; Q0<-0
;
EJECT
; SHIFT ENABLES
;
SE.EN:		EQU	B#0		; ENABLE SHIFTING
SE.DIS:		EQU	B#1		; DISABLE SHIFTING
;
;
;
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
; Am2904 STATUS REGISTER INSTRUCTION CODES
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; MACHINE STATUS REGISTER INSTRUCTION CODES
;    I5-I4-I3-I2-I1-I0 AND EZ-EC-EN-EOVR-CEM ENABLES
; MICRO STATUS REGISTER INSTRUCTION CODES
;    I5-I4-I3-I2-I1-I0 AND CEu ENABLE
;
; THE FOLLOWING TAKES THESE ALL TOGETHER - YOU MAY WISH TO DO THIS ANOTHER WAY
;
; ORDER: 543 210 ZCNOVR CEM CEu
;        Q#  Q#  H#     B#  B#
;
ONELEVEL:	EQU   	12Q#0000	; Y -> MSR; MSR -> USR
SET.MSR:	EQU	12Q#0101	; SET MACRO STATUS ONLY
SET.USR:	EQU	12Q#0176	; SET MICRO STATUS ONLY
SWAP.REG:	EQU	12Q#0200	; MSR <--> USR
;
LOAD.MSR:	EQU	12Q#2001	; ALU STATUS -> MSR
; THE ABOVE IS ONE OF SEVERAL CODES - YOU DON'T NEED THEM ALL!
;
LOAD.USR:	EQU	12Q#2076	; ALU STATUS -> USR
; DITTO!
;
LOAD.BOTH:	EQU	12Q#2000	; ALU -> MSR, USR
; AGAIN DITTO!
;
LDINVRTM: 	EQU	12Q#3001	; ALU -> MSR; Ic INVERTED
LDINVRTU:	EQU	12Q#3076	; ALU -> USR; Ic INVERTED
LOAD.INVERT:	EQU	12Q#3000	; ALU -> MSR, USR; Ic INVERTED
;
EJECT
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
; Am2904 CONDITION CODE OUTPUT INSTRUCTION CODES
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
; caution!  I5-I4-I3-I2-I1-I0 ARE ALSO USED FOR TESTING!!!!
; ENABLE TESTING VIA OEct ENABLE
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
TESTMZ:		EQU	12Q#4477  	; NO STATUS OPERATION
TESTMOVR:	EQU	12Q#4677	; NO STATUS OPERATION
TESTMC:		EQU	12Q#5277	; NO STATUS OPERATION
TESTMN:		EQU	12Q#5677	;
TEST.IOVR:	EQU	12Q#6677	;
TEST.IC:	EQU	12Q#7277	;
;
;
; TEST ENABLE
;
OECTEN:		EQU	B#0
OECTDIS:	EQU	B#1
;
;
; INSTRUCTION ENABLE
;
IEN.04:		EQU	B#0
IENDIS:		EQU	B#1
;
EJECT
AM2904:   DEF   42X,	12VQ#2001, 1VB#1,  1VB#0, 4VX,  1VB#1, 3X
; DEFAULTS              LOAD.MSR   OECTDIS OEYEN  X     SE.DIS
;
SHIFT.04:    DEF   56X,  4VX, 1B#0, 3X
;                       SHIFT SE.EN
TEST.04:     DEF   42X, 12VQ#7777, 1VB#0, 9X
;                      DISABLED   OECTEN
STATUS.04:   DEF   42X, 12VQ#2001, B#1, 1VB#0, 4X, B#1, 3X
;                      LOAD.MSR  NO CT OEYEN     SE.DIS
EJECT
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; Am2925 CYCLE LENGTH SELECT
; System Clock Generator and Driver
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
;
; THE FOLLOWING ARE THE CYCLE LENGTH CODES (PRELIM)  
; 
CLA:	EQU	Q#0	; 3 CLOCK PERIODS  	100ns AT 30MHz
CLB:	EQU	Q#1	; 4 			160ns AT 25MHz
CLC:	EQU	Q#5	; 5			200ns AT 25MHz
CLD:	EQU	Q#7	; 6			200ns AT 30MHz
CLE:	EQU	Q#3	; 7			280ns AT 25MHz
CLF:	EQU	Q#2	; 8			320ns AT 25MHz
CLG:	EQU	Q#6	; 9			300ns AT 30MHz
CLH:	EQU	Q#4     ; 10 CLOCK PERIODS	322ns AT 31MHz 
;					(max crystal frequency is 31MHz)
;
; OTHER CONTROL LINES FOR THE Am2925
; INCOMPLETELY DEFINED AT PRESENT (IN THIS FILE) 
;
FIRST.25:	EQU	B#1       	; 
LAST.25:	EQU	B#0		;
;
HALT:		EQU	B#00		;
NOHALT:		EQU	B#00		;
;
SINGLSTP:	EQU	B#00		;
RUN:		EQU	B#00		;
;
WAITREQ:	EQU	B#0		;
NOWAITRQ:	EQU	B#1		;
;
READY:		EQU	B#0		;
NOTREADY:	EQU	B#1		;
;
INITIALZE:	EQU	B#0		;
NO.INIT:	EQU	B#1		;
;
EJECT
; * * * * * * * * * * * * * * * * * * * * *
;
; Am2950/51
;
; Eight-Bit Bidirectional I/O Ports
;
; * * *
;
;
END










































