;PALASM Design Description

;---------------------------------- Declaration Segment ------------
TITLE    Glue logic (3) WR, RD, IO, selection
PATTERN  
REVISION 
AUTHOR   Dominic Thibodeau
COMPANY  
DATE     17/09/18

CHIP  dtglue3 PALCE16V8

;---------------------------------- PORT MAP---------------
;       Port            Description
;       0x40-0x43       PIT
;       0x60-0x67       UART

;---------------------------------- PIN Declarations ---------------
PIN  1          /MEM                                COMBINATORIAL;
PIN  4          A15                                 COMBINATORIAL;
PIN  5          A14                                 COMBINATORIAL;
PIN  6          A13                                 COMBINATORIAL;
PIN  8          /UOUT1                              COMBINATORIAL;
PIN  9          /SOUNDIN                            COMBINATORIAL;

PIN 10          GND;
PIN 20          VCC;

PIN 17          /ROMCE                              COMBINATORIAL;
PIN 16          /RAMCE                              COMBINATORIAL;
PIN 15          /PIT                                COMBINATORIAL;
PIN 14          /UART                               COMBINATORIAL;
PIN 13          SOUNDEN                             COMBINATORIAL;
PIN 12          SOUNDOUT                            COMBINATORIAL;

;----------------------------------- Boolean Equation Segment ------
EQUATIONS

SOUNDEN = UOUT1
SOUNDOUT = SOUNDIN

ROMCE = /A15 * MEM
RAMCE = A15 * MEM

PIT =  (/A15 * A14 * /A13) * (/MEM)
UART = (/A15 * A14 *  A13) * (/MEM)

;----------------------------------- Simulation Segment ------------
SIMULATION

TRACE_ON MEM A15 A14 A13 ROMCE RAMCE PIT UART SOUNDEN

SETF /UOUT1
SETF UOUT1

SETF /A15
SETF /MEM
SETF MEM

SETF A15
SETF /MEM
SETF MEM

TRACE_OFF


;-------------------------------------------------------------------
