ep994a Project Status (04/23/2018 - 18:37:40)
Project File: | ep994a.xise | Parser Errors: | No Errors
Module Name: | ep994a | Implementation State: | Programming File Generated
Target Device: | xc6slx9-2ftg256 |

- Errors:

No Errors
Product Version: | ISE 14.7 |

- Warnings:

191 Warnings (76 new)
Design Goal: | Balanced |

- Routing Results:

All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

All Constraints Met
Environment: | System Settings |

- Final Timing Score:

0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 1,478 | 11,440 | 12% |
Number used as Flip Flops | 1,474 |  |  |
Number used as Latches | 3 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 1 |  |  |
Number of Slice LUTs | 3,028 | 5,720 | 52% |
Number used as logic | 3,003 | 5,720 | 52% |
Number using O6 output only | 2,418 |  |  |
Number using O5 output only | 124 |  |  |
Number using O5 and O6 | 461 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 10 | 1,440 | 1% |
Number used as Dual Port RAM | 8 |  |  |
Number using O6 output only | 4 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 4 |  |  |
Number used as Single Port RAM | 2 |  |  |
Number using O6 output only | 2 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used as Shift Register | 0 |  |  |
Number used exclusively as route-thrus | 15 |  |  |
Number with same-slice register load | 7 |  |  |
Number with same-slice carry load | 8 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 1,005 | 1,430 | 70% |
Number of MUXCYs used | 408 | 2,860 | 14% |
Number of LUT Flip Flop pairs used | 3,221 |  |  |
Number with an unused Flip Flop | 1,867 | 3,221 | 57% |
Number with an unused LUT | 193 | 3,221 | 5% |
Number of fully used LUT-FF pairs | 1,161 | 3,221 | 36% |
Number of unique control sets | 152 |  |  |
Number of slice register sites lost to control set restrictions | 517 | 11,440 | 4% |
Number of bonded IOBs | 121 | 186 | 65% |
Number of LOCed IOBs | 121 | 121 | 100% |
Number of RAMB16BWERs | 10 | 32 | 31% |
Number of RAMB8BWERs | 0 | 64 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 1 | 32 | 3% |
Number used as BUFIO2s | 1 |  |  |
Number used as BUFIO2_2CLKs | 0 |  |  |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 1 | 32 | 3% |
Number used as BUFIO2FBs | 1 |  |  |
Number used as BUFIO2FB_2CLKs | 0 |  |  |
Number of BUFG/BUFGMUXs | 3 | 16 | 18% |
Number used as BUFGs | 3 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 1 | 4 | 25% |
Number used as DCMs | 1 |  |  |
Number used as DCM_CLKGENs | 0 |  |  |
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 1 | 16 | 6% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 2 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 4.34 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | ma 23. huhti 18:35:30 2018 | 0 | 173 Warnings (58 new) | 54 Infos (35 new)
Translation Report | Current | ma 23. huhti 18:35:37 2018 | 0 | 2 Warnings (2 new) | 1 Info (0 new)
Map Report | Current | ma 23. huhti 18:36:28 2018 | 0 | 3 Warnings (3 new) | 8 Infos (2 new)
Place and Route Report | Current | ma 23. huhti 18:36:57 2018 | 0 | 10 Warnings (10 new) | 0
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | ma 23. huhti 18:37:04 2018 | 0 | 0 | 3 Infos (0 new)
Bitgen Report | Current | ma 23. huhti 18:37:19 2018 | 0 | 3 Warnings (3 new) | 1 Info (0 new)

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Out of Date | ke 27. syys 16:19:04 2017
WebTalk Report | Out of Date | ma 23. huhti 18:37:20 2018
WebTalk Log File | Out of Date | ma 23. huhti 18:37:40 2018

Date Generated: 04/23/2018 - 18:39:35