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## Code2Graphics generation results

Created on Thu 2016-06-02 at 01:21:59

CODE2GRAPHICS SETTINGS:
Multipage block diagrams generation: DISABLED
Hierarchical state diagrams generation: DISABLED
Destination directory: C:\My_Designs\Processor\Processor\src
INTERMEDIATE FILES GENERATION:
Analyzing intermediate file C:\Users\GREENT~1\AppData\Local\Temp\Processor\Processor.erf ...
File: C:\My_Designs\Processor\Processor\src\ADDER.vhd
Checking Entity "ADDER"
Checking Architecture "BEHV" of Entity "ADDER"
File: C:\My_Designs\Processor\Processor\src\ADDSUB.vhd
Checking Entity "ADDSUB"
Checking Architecture "BEHV" of Entity "ADDSUB"
File: C:\My_Designs\Processor\Processor\src\CONTROL.vhd
Checking Entity "CONTROL"
Checking Architecture "BEHV" of Entity "CONTROL"
File: C:\My_Designs\Processor\Processor\src\COUNTER.vhd
Checking Entity "COUNTER"
Checking Architecture "BEHV" of Entity "COUNTER"
File: C:\My_Designs\Processor\Processor\src\DECODER_3_8.vhd
Checking Entity "DECODER_3_8"
Checking Architecture "BEHV" of Entity "DECODER_3_8"
File: C:\My_Designs\Processor\Processor\src\DEMONSTRATION.vhd
Checking Entity "DEMONSTRATION"
Checking Architecture "TB" of Entity "DEMONSTRATION"
File: C:\My_Designs\Processor\Processor\src\IR.vhd
Checking Entity "IR"
Checking Architecture "BEHV" of Entity "IR"
File: C:\My_Designs\Processor\Processor\src\MUX10TO1.vhd
Checking Entity "MUX10TO1"
Checking Architecture "behv" of Entity "mux10to1"
File: C:\My_Designs\Processor\Processor\src\PROCESSOR.vhd
Checking Entity "PROCESSOR"
Checking Architecture "BEHV" of Entity "PROCESSOR"
File: C:\My_Designs\Processor\Processor\src\REGISTER_9.vhd
Checking Entity "REGISTER_9"
Checking Architecture "BEHV" of Entity "REGISTER_9"
File: C:\My_Designs\Processor\Processor\src\REGISTER_16.vhd
Checking Entity "REGISTER_16"
Checking Architecture "BEHV" of Entity "REGISTER_16"
File: C:\My_Designs\Processor\Processor\src\SUB.vhd
Checking Entity "SUB"
Checking Architecture "BEHV" of Entity "SUB"
File: C:\My_Designs\Processor\Processor\src\SUBTRACTOR.vhd
Checking Entity "SUBTRACTOR"
Checking Architecture "BEHV" of Entity "SUBTRACTOR"
File: C:\My_Designs\Processor\Processor\src\T_FF.vhd
Checking Entity "T_FF"
Checking Architecture "BEHV" of Entity "T_FF"
File: C:\My_Designs\Processor\Processor\src\TEST_CONTROL.vhd
Checking Entity "TEST_CONTROL"
Checking Architecture "TB" of Entity "TEST_CONTROL"
File: C:\My_Designs\Processor\Processor\src\TEST_COUNTER.vhd
Checking Entity "TEST_COUNTER"
Checking Architecture "TB" of Entity "TEST_COUNTER"
File: C:\My_Designs\Processor\Processor\src\TEST_PROCESSOR.vhd
Checking Entity "TEST_PROCESSOR"
Checking Architecture "TB" of Entity "TEST_PROCESSOR"
File: C:\My_Designs\Processor\Processor\src\TESTMUX.vhd
Checking Entity "TESTMUX"
Checking Architecture "TB" of Entity "TESTMUX"
Checking Configuration "CFG_TB"
Checking success 0 Errors 0 Warnings Analysis time : 0.5 [s]
Finished successfully.
DIAGRAM FILES GENERATION:
Cannot convert .\src\ADDER.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\ADDSUB.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\CONTROL.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\COUNTER.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\DECODER_3_8.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\DEMONSTRATION.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\IR.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\MUX10TO1.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\PROCESSOR.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\REGISTER_16.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\REGISTER_9.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\SUBTRACTOR.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\SUB.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\TESTMUX.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\TEST_CONTROL.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\TEST_COUNTER.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\TEST_PROCESSOR.vhd to state diagram because a state machine pattern could not be recognized.
Cannot convert .\src\T_FF.vhd to state diagram because a state machine pattern could not be recognized.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7734748.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\773474A.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\773474C.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\773474E.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7754760.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7754762.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7754764.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7754766.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7754768.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\775476A.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\775476C.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7754770.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\775476E.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7764789.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7764783.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7764785.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7764787.tmp ...
Temporary block diagram file has been successfully generated.
Generating temporary block diagram file C:\Users\GREENT~1\AppData\Local\Temp\7754772.tmp ...
Temporary block diagram file has been successfully generated.
Diagram file(s) generation completed in 0.438 seconds.
File C:\My_Designs\Processor\Processor\src\adder.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\addsub.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\control.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\counter.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\decoder_3_8.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\demonstration.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\ir.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\mux10to1.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\processor.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\register_16.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\register_9.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\subtractor.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\sub.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\testmux.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\test_control.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\test_counter.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\test_processor.bde has been successfully generated.
File C:\My_Designs\Processor\Processor\src\t_ff.bde has been successfully generated.
18 unit(s) converted to Block Diagram(s)
0 unit(s) converted to State Diagram(s)
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