--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone II" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" clkselect ena inclk outclk
--VERSION_BEGIN 8.0 cbx_altclkbuf 2008:02:23:252825 cbx_cycloneii 2008:02:23:252825 cbx_lpm_add_sub 2008:03:09:257947 cbx_lpm_compare 2008:02:23:252825 cbx_lpm_decode 2008:02:23:252825 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944 cbx_stratix 2008:02:23:252825 cbx_stratixii 2008:02:23:252825 cbx_stratixiii 2008:04:23:278548  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.


FUNCTION cycloneii_clkctrl (clkselect[1..0], ena, inclk[3..0])
WITH ( clock_type, ena_register_mode)
RETURNS ( outclk);

--synthesis_resources = clkctrl 1 
SUBDESIGN c_lock_altclkctrl_lei
( 
	clkselect[1..0]	:	input;
	ena	:	input;
	inclk[3..0]	:	input;
	outclk	:	output;
) 
VARIABLE 
	clkctrl1 : cycloneii_clkctrl
		WITH (
			clock_type = "Global Clock",
			ena_register_mode = "falling edge"
		);
	clkselect_wire[1..0]	: WIRE;
	inclk_wire[3..0]	: WIRE;

BEGIN 
	clkctrl1.clkselect[] = clkselect_wire[];
	clkctrl1.ena = ena;
	clkctrl1.inclk[] = inclk_wire[];
	clkselect_wire[] = ( clkselect[]);
	inclk_wire[] = ( inclk[]);
	outclk = clkctrl1.outclk;
END;
--VALID FILE
