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set device xc6slx16csg324-2
set projName dualport32k
set design dualport32k
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module dualport32k_exdes
add_files -norecurse {../../example_design/dualport32k_exdes.vhd}
add_files -norecurse {./dualport32k.ngc}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/dualport32k_exdes.xdc}
set_property top dualport32k_exdes [get_property srcset [current_run]]
synth_design
opt_design 
place_design 
route_design 
write_sdf -rename_top_module dualport32k_exdes -file routed.sdf 
write_vhdl -mode sim routed.vhd
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
