<<<<<<< HEAD toplevel Project Status (02/20/2019 - 17:51:58)
======= | toplevel Project Status (02/24/2019 - 12:39:08) >>>>>>> byte_sram
Project File: | cvAtari2600.xise | Parser Errors: | No Errors
Module Name: | toplevel | Implementation State: | Programming File Generated
Target Device: | xc6slx16-2csg324 |

- Errors:

Product Version: | ISE 14.7 |

- Warnings:

Design Goal: | Balanced |

- Routing Results:

<<<<<<< HEAD All Signals Completely Routed ======= All Signals Completely Routed >>>>>>> byte_sram
Design Strategy: | Xilinx Default (unlocked) |

- Timing Constraints:

<<<<<<< HEAD All Constraints Met ======= X 3 Failing Constraints >>>>>>> byte_sram
Environment: | <<<<<<< HEAD System Settings |

- Final Timing Score:

0 (Timing Report) ======= System Settings

- Final Timing Score:

226094 (Timing Report) >>>>>>> byte_sram

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 1,766 | 18,224 | 9% |
Number used as Flip Flops | 1,748 |  |  |
Number used as Latches | 1 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 17 |  |  |
Number of Slice LUTs | 3,075 | 9,112 | 33% |
Number used as logic | 2,975 | 9,112 | 32% |
Number using O6 output only | 2,303 |  |  |
Number using O5 output only | 188 |  |  |
Number using O5 and O6 | 484 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 69 | 2,176 | 3% |
Number used as Dual Port RAM | 24 |  |  |
Number using O6 output only | 4 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 20 |  |  |
Number used as Single Port RAM | 16 |  |  |
Number using O6 output only | 16 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used as Shift Register | 29 |  |  |
Number using O6 output only | 6 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 23 |  |  |
Number used exclusively as route-thrus | 31 |  |  |
Number with same-slice register load | 10 |  |  |
Number with same-slice carry load | 21 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 1,115 | 2,278 | 48% |
Number of MUXCYs used | 540 | 4,556 | 11% |
Number of LUT Flip Flop pairs used | 3,374 |  |  |
Number with an unused Flip Flop | 1,742 | 3,374 | 51% |
Number with an unused LUT | 299 | 3,374 | 8% |
Number of fully used LUT-FF pairs | 1,333 | 3,374 | 39% |
Number of unique control sets | 149 |  |  |
Number of slice register sites lost to control set restrictions | 483 | 18,224 | 2% |
<<<<<<< HEAD
Number of bonded IOBs =======
Number of bonded IOBs >>>>>>> byte_sram | 119 | 232 | 51% |
Number of LOCed IOBs | 119 | 119 | 100% |
IOB Flip Flops | 4 |  |  |
IOB Master Pads | 4 |  |  |
IOB Slave Pads | 4 |  |  |
Number of RAMB16BWERs | 26 | 32 | 81% |
Number of RAMB8BWERs | 2 | 64 | 3% |
Number of BUFIO2/BUFIO2_2CLKs | 2 | 32 | 6% |
Number used as BUFIO2s | 2 |  |  |
Number used as BUFIO2_2CLKs | 0 |  |  |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 2 | 32 | 6% |
Number used as BUFIO2FBs | 2 |  |  |
Number used as BUFIO2FB_2CLKs | 0 |  |  |
Number of BUFG/BUFGMUXs | 8 | 16 | 50% |
Number used as BUFGs | 8 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 2 | 4 | 50% |
Number used as DCMs | 2 |  |  |
Number used as DCM_CLKGENs | 0 |  |  |
Number of ILOGIC2/ISERDES2s | 0 | 248 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 248 | 0% |
Number of OLOGIC2/OSERDES2s | 4 | 248 | 1% |
Number used as OLOGIC2s | 4 |  |  |
Number used as OSERDES2s | 0 |  |  |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 5 | 32 | 15% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 2 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 4.11 |  |  |

Performance Summary | [-]
Final Timing Score: | 226094 (Setup: 226094, Hold: 0, Component Switching Limit: 0) | Pinout Data: <<<<<<< HEAD | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report ======= | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report >>>>>>> byte_sram
Timing Constraints: | <<<<<<< HEAD All Constraints Met ======= X 3 Failing Constraints >>>>>>> byte_sram |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
<<<<<<< HEAD
Synthesis Report | Current | ke 20. helmi 17:48:41 2019 |  |  |
Translation Report | Current | ke 20. helmi 17:48:57 2019 | 0 | 0 | 1 Info (1 new)
Map Report | Current | ke 20. helmi 17:50:10 2019 | 0 | 1 Warning (0 new) | 9 Infos (2 new)
Place and Route Report | Current | ke 20. helmi 17:50:50 2019 | 0 | 22 Warnings (2 new) | 0
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | ke 20. helmi 17:51:07 2019 | 0 | 0 | 3 Infos (0 new)
Bitgen Report | Current | ke 20. helmi 17:51:47 2019 | 0 | 1 Warning (0 new) | 2 Infos (1 new)
=======
Synthesis Report | Current | ma 4. maalis 19:15:12 2019 |  |  |
Translation Report | Current | ma 4. maalis 19:15:29 2019 | 0 | 0 | 5 Infos (0 new)
Map Report | Current | ma 4. maalis 19:17:13 2019 | 0 | 24 Warnings (0 new) | 11 Infos (0 new)
Place and Route Report | Current | ma 4. maalis 19:18:20 2019 | 0 | 26 Warnings (0 new) | 0
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | ma 4. maalis 19:18:40 2019 | 0 | 0 | 3 Infos (0 new)
Bitgen Report | Current | ma 4. maalis 19:19:26 2019 | 0 | 23 Warnings (0 new) | 3 Infos (0 new)
>>>>>>> byte_sram

Secondary Reports | [-]
Report Name | Status | Generated
<<<<<<< HEAD
WebTalk Report | Current | ke 20. helmi 17:51:53 2019
WebTalk Log File | Current | ke 20. helmi 17:51:57 2019

Date Generated: 02/20/2019 - 17:51:58
=======
WebTalk Report Current ma 4. maalis 19:37:31 2019
WebTalk Log File Current ma 4. maalis 19:37:34 2019
Date Generated: 03/04/2019 - 19:57:25
>>>>>>> byte_sram