
#   Z80 CPU Emulator.
#   https://github.com/kosarev/z80
#
#   Copyright (c) 2019 Ivan Kosarev <ivan@kosarev.info>
#   Published under the MIT license.

# ACI n
ce16 aci 0x16
 0 fetch ce at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read 16 at 0001
 4   get_pc_on_imm8_read 0001
 4   read 16 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 get_a 00
 7 get_f 00
 7 set_a 00 -> 16
 7 set_f 00 -> 00
 7 done

# ADD r
87 add a
 0 fetch 87 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_a 00
 4 get_a 00
 4 set_a 00 -> 00
 4 set_f 00 -> 44
 4 done

# ADC r
89 adc c
 0 fetch 89 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_c 00
 4 get_a 00
 4 get_f 00
 4 set_a 00 -> 00
 4 set_f 00 -> 44
 4 done

# ADI n
c616 adi 0x16
 0 fetch c6 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read 16 at 0001
 4   get_pc_on_imm8_read 0001
 4   read 16 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 get_a 00
 7 set_a 00 -> 16
 7 set_f 00 -> 00
 7 done

# ANA r
a7 ana a
 0 fetch a7 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_a 00
 4 get_a 00
 4 set_a 00 -> 00
 4 set_f 00 -> 44
 4 done

# ANI n
e616 ani 0x16
 0 fetch e6 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read 16 at 0001
 4   get_pc_on_imm8_read 0001
 4   read 16 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 get_a 00
 7 set_a 00 -> 00
 7 set_f 00 -> 44
 7 done

# CALL nn
cddf0e call 0x0edf
 0 fetch cd at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm16_read 0edf at 0001
 4   get_pc_on_imm16_read 0001
 4   read df at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   read 0e at 0002
 7     set_addr_bus 0001 -> 0002
 9     mreq_wait 0002
10   set_pc_on_imm16_read 0001 -> 0003
10 read_cycle_extra_1t
11 get_sp 0000
11 write 00 -> 00 at ffff
11   set_addr_bus 0002 -> ffff
13   mreq_wait ffff
14 write 00 -> 03 at fffe
14   set_addr_bus ffff -> fffe
16   mreq_wait fffe
17 set_sp 0000 -> fffe
17 set_wz 0000 -> 0edf
17 set_pc_on_call 0003 -> 0edf
17 done

eddf0e xcall 0xed, 0x0edf
dddf0e xcall 0xdd, 0x0edf
fddf0e xcall 0xfd, 0x0edf

# Ccc, nn
c4550c cnz 0x0c55
 0 fetch c4 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 imm16_read 0c55 at 0001
 5   get_pc_on_imm16_read 0001
 5   read 55 at 0001
 5     set_addr_bus 0000 -> 0001
 7     mreq_wait 0001
 8   read 0c at 0002
 8     set_addr_bus 0001 -> 0002
10     mreq_wait 0002
11   set_pc_on_imm16_read 0001 -> 0003
11 get_f 00
11 get_sp 0000
11 write 00 -> 00 at ffff
11   set_addr_bus 0002 -> ffff
13   mreq_wait ffff
14 write 00 -> 03 at fffe
14   set_addr_bus ffff -> fffe
16   mreq_wait fffe
17 set_sp 0000 -> fffe
17 set_wz 0000 -> 0c55
17 set_pc_on_call 0003 -> 0c55
17 done

# CMA
2f cma
 0 fetch 2f at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_a 00
 4 set_a 00 -> ff
 4 done

# CMC
3f cmc
 0 fetch 3f at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_f 00
 4 set_f 00 -> 01
 4 done

# CMP r
bc cmp h
 0 fetch bc at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_h 00
 4 get_a 00
 4 set_f 00 -> 54
 4 done

# CPI n
fe16 cpi 0x16
 0 fetch fe at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read 16 at 0001
 4   get_pc_on_imm8_read 0001
 4   read 16 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 get_a 00
 7 set_f 00 -> 81
 7 done

# DAA
27 daa
 0 fetch 27 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_a 00
 4 get_f 00
 4 set_a 00 -> 00
 4 set_f 00 -> 44
 4 done

# DAD rp
19 dad d
 0 fetch 19 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 3t_exec
 7 3t_exec
10 get_l 00
10 get_h 00
10 get_e 00
10 get_d 00
10 get_f 00
10 set_wz 0000 -> 0001
10 set_l 00 -> 00
10 set_h 00 -> 00
10 set_f 00 -> 00
10 done

# DCR r
35 dcr m
 0 fetch 35 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_l 00
 4 get_h 00
 4 read 35 at 0000
 4   set_addr_bus 0000 -> 0000
 6   mreq_wait 0000
 7 get_f 00
 7 get_l 00
 7 get_h 00
 7 write 35 -> 34 at 0000
 7   set_addr_bus 0000 -> 0000
 9   mreq_wait 0000
10 set_f 00 -> 10
10 done

# DCX rp
2b dcx h
 0 fetch 2b at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 get_l 00
 5 get_h 00
 5 set_l 00 -> ff
 5 set_h 00 -> ff
 5 done

# DI
f3 di
 0 fetch f3 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 set_iff_on_di 0 -> 0
 4 done

# EI
fb ei
 0 fetch fb at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 set_iff_on_ei 0 -> 1
 4 disable_int
 4 done

# HLT
76 hlt
 0 fetch 76 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_3t
 7 done

# JMP nn
c3cdab jmp 0xabcd
 0 fetch c3 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm16_read abcd at 0001
 4   get_pc_on_imm16_read 0001
 4   read cd at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   read ab at 0002
 7     set_addr_bus 0001 -> 0002
 9     mreq_wait 0002
10   set_pc_on_imm16_read 0001 -> 0003
10 set_wz 0000 -> abcd
10 set_pc_on_jump 0003 -> abcd
10 done

cbcdab xjmp 0xcb, 0xabcd

# Jcc nn
d2d90a jnc 0x0ad9
 0 fetch d2 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm16_read 0ad9 at 0001
 4   get_pc_on_imm16_read 0001
 4   read d9 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   read 0a at 0002
 7     set_addr_bus 0001 -> 0002
 9     mreq_wait 0002
10   set_pc_on_imm16_read 0001 -> 0003
10 get_f 00
10 set_wz 0000 -> 0ad9
10 set_pc_on_jump 0003 -> 0ad9
10 done

# IN n
dbfe in 0xfe
 0 fetch db at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read fe at 0001
 4   get_pc_on_imm8_read 0001
 4   read fe at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 input at 00fe
 9   iorq_wait 00fe
10 set_a 00 -> ff
10 done

# INR r
04 inr b
 0 fetch 04 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 get_b 00
 5 get_f 00
 5 set_b 00 -> 01
 5 set_f 00 -> 00
 5 done

# INR M
34 inr m
 0 fetch 34 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_l 00
 4 get_h 00
 4 read 34 at 0000
 4   set_addr_bus 0000 -> 0000
 6   mreq_wait 0000
 7 get_f 00
 7 get_l 00
 7 get_h 00
 7 write 34 -> 35 at 0000
 7   set_addr_bus 0000 -> 0000
 9   mreq_wait 0000
10 set_f 00 -> 04
10 done

# INX rp
23 inx h
 0 fetch 23 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 get_l 00
 5 get_h 00
 5 set_l 00 -> 01
 5 set_h 00 -> 00
 5 done

# LDA nn
3a8d5c lda 0x5c8d
 0 fetch 3a at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm16_read 5c8d at 0001
 4   get_pc_on_imm16_read 0001
 4   read 8d at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   read 5c at 0002
 7     set_addr_bus 0001 -> 0002
 9     mreq_wait 0002
10   set_pc_on_imm16_read 0001 -> 0003
10 set_wz 0000 -> 5c8e
10 read 00 at 5c8d
10   set_addr_bus 0002 -> 5c8d
12   mreq_wait 5c8d
13 set_a 00 -> 00
13 done

# LDAX rp
1a ldax d
 0 fetch 1a at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_e 00
 4 get_d 00
 4 set_wz 0000 -> 0001
 4 read 1a at 0000
 4   set_addr_bus 0000 -> 0000
 6   mreq_wait 0000
 7 set_a 00 -> 1a
 7 done

# LHLD nn
2ab25c lhld 0x5cb2
 0 fetch 2a at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm16_read 5cb2 at 0001
 4   get_pc_on_imm16_read 0001
 4   read b2 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   read 5c at 0002
 7     set_addr_bus 0001 -> 0002
 9     mreq_wait 0002
10   set_pc_on_imm16_read 0001 -> 0003
10 read 00 at 5cb2
10   set_addr_bus 0002 -> 5cb2
12   mreq_wait 5cb2
13 set_wz 0000 -> 5cb3
13 read 00 at 5cb3
13   set_addr_bus 5cb2 -> 5cb3
15   mreq_wait 5cb3
16 set_l 00 -> 00
16 set_h 00 -> 00
16 done

# LXI rp, nn
115634 lxi d, 0x3456
 0 fetch 11 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm16_read 3456 at 0001
 4   get_pc_on_imm16_read 0001
 4   read 56 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   read 34 at 0002
 7     set_addr_bus 0001 -> 0002
 9     mreq_wait 0002
10   set_pc_on_imm16_read 0001 -> 0003
10 set_e 00 -> 56
10 set_d 00 -> 34
10 done

# ORA r
b3 ora e
 0 fetch b3 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_e 00
 4 get_a 00
 4 set_a 00 -> 00
 4 set_f 00 -> 44
 4 done

# ORI n
f616 ori 0x16
 0 fetch f6 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read 16 at 0001
 4   get_pc_on_imm8_read 0001
 4   read 16 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 get_a 00
 7 set_a 00 -> 16
 7 set_f 00 -> 00
 7 done

# OUT n
d3ab out 0xab
 0 fetch d3 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read ab at 0001
 4   get_pc_on_imm8_read 0001
 4   read ab at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 get_a 00
 7 output 00 at ab
 9   iorq_wait 00ab
10 done

# PCHL
e9 pchl
 0 fetch e9 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 get_l 00
 5 get_h 00
 5 set_pc_on_jump 0001 -> 0000
 5 done

# RAL
17 ral
 0 fetch 17 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_a 00
 4 get_f 00
 4 set_a 00 -> 00
 4 set_f 00 -> 00
 4 done

# RAR
1f rar
 0 fetch 1f at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_a 00
 4 get_f 00
 4 set_a 00 -> 00
 4 set_f 00 -> 00
 4 done

# RLC
07 rlc
 0 fetch 07 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_a 00
 4 get_f 00
 4 set_a 00 -> 00
 4 set_f 00 -> 00
 4 done

# RRC
0f rrc
 0 fetch 0f at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_a 00
 4 get_f 00
 4 set_a 00 -> 00
 4 set_f 00 -> 00
 4 done

# SBB r
9f sbb a
 0 fetch 9f at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_a 00
 4 get_a 00
 4 get_f 00
 4 set_a 00 -> 00
 4 set_f 00 -> 54
 4 done

# SBI n
de16 sbi 0x16
 0 fetch de at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read 16 at 0001
 4   get_pc_on_imm8_read 0001
 4   read 16 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 get_a 00
 7 get_f 00
 7 set_a 00 -> ea
 7 set_f 00 -> 81
 7 done

# SPHL
f9 sphl
 0 fetch f9 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 get_l 00
 5 get_h 00
 5 set_sp 0000 -> 0000
 5 done

# SUB r
91 sub c
 0 fetch 91 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_c 00
 4 get_a 00
 4 set_a 00 -> 00
 4 set_f 00 -> 54
 4 done

# SUI n
d616 sui 0x16
 0 fetch d6 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read 16 at 0001
 4   get_pc_on_imm8_read 0001
 4   read 16 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 get_a 00
 7 set_a 00 -> ea
 7 set_f 00 -> 81
 7 done

# MVI r, n
3eaf mvi a, 0xaf
 0 fetch 3e at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read af at 0001
 4   get_pc_on_imm8_read 0001
 4   read af at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 set_a 00 -> af
 7 done

# MOV r, r
47 mov b, a
 0 fetch 47 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 get_a 00
 5 set_b 00 -> 00
 5 done

# NOP
00 nop
 0 fetch 00 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 done

08 xnop 0x08
10 xnop 0x10
18 xnop 0x18
20 xnop 0x20
28 xnop 0x28
30 xnop 0x30
38 xnop 0x38

# POP rp2
c1 pop b
 0 fetch c1 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_sp 0000
 4 read c1 at 0000
 4   set_addr_bus 0000 -> 0000
 6   mreq_wait 0000
 7 read 00 at 0001
 7   set_addr_bus 0000 -> 0001
 9   mreq_wait 0001
10 set_sp 0000 -> 0002
10 set_c 00 -> c1
10 set_b 00 -> 00
10 done

# PUSH rp2
c5 push b
 0 fetch c5 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 get_c 00
 5 get_b 00
 5 get_sp 0000
 5 write 00 -> 00 at ffff
 5   set_addr_bus 0000 -> ffff
 7   mreq_wait ffff
 8 write 00 -> 00 at fffe
 8   set_addr_bus ffff -> fffe
10   mreq_wait fffe
11 set_sp 0000 -> fffe
11 done

# RET
c9 ret
 0 fetch c9 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_sp 0000
 4 read c9 at 0000
 4   set_addr_bus 0000 -> 0000
 6   mreq_wait 0000
 7 read 00 at 0001
 7   set_addr_bus 0000 -> 0001
 9   mreq_wait 0001
10 set_sp 0000 -> 0002
10 set_wz 0000 -> 00c9
10 set_pc_on_return 0001 -> 00c9
10 done

d9 xret 0xd9

# Rcc
c0 rnz
 0 fetch c0 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 get_f 00
 5 get_sp 0000
 5 read c0 at 0000
 5   set_addr_bus 0000 -> 0000
 7   mreq_wait 0000
 8 read 00 at 0001
 8   set_addr_bus 0000 -> 0001
10   mreq_wait 0001
11 set_sp 0000 -> 0002
11 set_wz 0000 -> 00c0
11 set_pc_on_return 0001 -> 00c0
11 done

# RST nn
d7 rst 0x0010
 0 fetch d7 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 get_sp 0000
 5 write 00 -> 00 at ffff
 5   set_addr_bus 0000 -> ffff
 7   mreq_wait ffff
 8 write 00 -> 01 at fffe
 8   set_addr_bus ffff -> fffe
10   mreq_wait fffe
11 set_sp 0000 -> fffe
11 set_wz 0000 -> 0010
11 set_pc_on_call 0001 -> 0010
11 done

# STC
37 stc
 0 fetch 37 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_f 00
 4 set_f 00 -> 01
 4 done

# SHLD nn
227b5c shld 0x5c7b
 0 fetch 22 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm16_read 5c7b at 0001
 4   get_pc_on_imm16_read 0001
 4   read 7b at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   read 5c at 0002
 7     set_addr_bus 0001 -> 0002
 9     mreq_wait 0002
10   set_pc_on_imm16_read 0001 -> 0003
10 get_l 00
10 get_h 00
10 write 00 -> 00 at 5c7b
10   set_addr_bus 0002 -> 5c7b
12   mreq_wait 5c7b
13 set_wz 0000 -> 5c7c
13 write 00 -> 00 at 5c7c
13   set_addr_bus 5c7b -> 5c7c
15   mreq_wait 5c7c
16 done

# STA nn
328d5c sta 0x5c8d
 0 fetch 32 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm16_read 5c8d at 0001
 4   get_pc_on_imm16_read 0001
 4   read 8d at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   read 5c at 0002
 7     set_addr_bus 0001 -> 0002
 9     mreq_wait 0002
10   set_pc_on_imm16_read 0001 -> 0003
10 get_a 00
10 set_wz 0000 -> 008e
10 write 00 -> 00 at 5c8d
10   set_addr_bus 0002 -> 5c8d
12   mreq_wait 5c8d
13 done

# STAX rp
12 stax d
 0 fetch 12 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_e 00
 4 get_d 00
 4 get_a 00
 4 set_wz 0000 -> 0001
 4 write 12 -> 00 at 0000
 4   set_addr_bus 0000 -> 0000
 6   mreq_wait 0000
 7 done

# XCHG
eb xchg
 0 fetch eb at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 fetch_cycle_extra_1t
 5 done

# XRA r
af xra a
 0 fetch af at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_a 00
 4 get_a 00
 4 set_a 00 -> 00
 4 set_f 00 -> 44
 4 done

# XRI n
ee16 xri 0x16
 0 fetch ee at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 imm8_read 16 at 0001
 4   get_pc_on_imm8_read 0001
 4   read 16 at 0001
 4     set_addr_bus 0000 -> 0001
 6     mreq_wait 0001
 7   set_pc_on_imm8_read 0001 -> 0002
 7 get_a 00
 7 set_a 00 -> 16
 7 set_f 00 -> 00
 7 done

# XTHL
e3 xthl
 0 fetch e3 at 0000
 0   get_pc_on_fetch 0000
 0   set_addr_bus 0000 -> 0000
 2   mreq_wait 0000
 4   set_pc_on_fetch 0000 -> 0001
 4 get_sp 0000
 4 read e3 at 0000
 4   set_addr_bus 0000 -> 0000
 6   mreq_wait 0000
 7 read 00 at 0001
 7   set_addr_bus 0000 -> 0001
 9   mreq_wait 0001
10 get_l 00
10 get_h 00
10 write 00 -> 00 at 0001
10   set_addr_bus 0001 -> 0001
12   mreq_wait 0001
13 write e3 -> 00 at 0000
13   set_addr_bus 0001 -> 0000
15   mreq_wait 0000
16 write_cycle_extra_2t
18 set_wz 0000 -> 00e3
18 set_l 00 -> e3
18 set_h 00 -> 00
18 done

# All instructions.
00 nop
010000 lxi b, 0x0000
02 stax b
03 inx b
04 inr b
05 dcr b
0600 mvi b, 0x00
07 rlc
08 xnop 0x08
09 dad b
0a ldax b
0b dcx b
0c inr c
0d dcr c
0e00 mvi c, 0x00
0f rrc
10 xnop 0x10
110000 lxi d, 0x0000
12 stax d
13 inx d
14 inr d
15 dcr d
1600 mvi d, 0x00
17 ral
18 xnop 0x18
19 dad d
1a ldax d
1b dcx d
1c inr e
1d dcr e
1e00 mvi e, 0x00
1f rar
20 xnop 0x20
210000 lxi h, 0x0000
220000 shld 0x0000
23 inx h
24 inr h
25 dcr h
2600 mvi h, 0x00
27 daa
28 xnop 0x28
29 dad h
2a0000 lhld 0x0000
2b dcx h
2c inr l
2d dcr l
2e00 mvi l, 0x00
2f cma
30 xnop 0x30
310000 lxi sp, 0x0000
320000 sta 0x0000
33 inx sp
34 inr m
35 dcr m
3600 mvi m, 0x00
37 stc
38 xnop 0x38
39 dad sp
3a0000 lda 0x0000
3b dcx sp
3c inr a
3d dcr a
3e00 mvi a, 0x00
3f cmc
40 mov b, b
41 mov b, c
42 mov b, d
43 mov b, e
44 mov b, h
45 mov b, l
46 mov b, m
47 mov b, a
48 mov c, b
49 mov c, c
4a mov c, d
4b mov c, e
4c mov c, h
4d mov c, l
4e mov c, m
4f mov c, a
50 mov d, b
51 mov d, c
52 mov d, d
53 mov d, e
54 mov d, h
55 mov d, l
56 mov d, m
57 mov d, a
58 mov e, b
59 mov e, c
5a mov e, d
5b mov e, e
5c mov e, h
5d mov e, l
5e mov e, m
5f mov e, a
60 mov h, b
61 mov h, c
62 mov h, d
63 mov h, e
64 mov h, h
65 mov h, l
66 mov h, m
67 mov h, a
68 mov l, b
69 mov l, c
6a mov l, d
6b mov l, e
6c mov l, h
6d mov l, l
6e mov l, m
6f mov l, a
70 mov m, b
71 mov m, c
72 mov m, d
73 mov m, e
74 mov m, h
75 mov m, l
76 hlt
77 mov m, a
78 mov a, b
79 mov a, c
7a mov a, d
7b mov a, e
7c mov a, h
7d mov a, l
7e mov a, m
7f mov a, a
80 add b
81 add c
82 add d
83 add e
84 add h
85 add l
86 add m
87 add a
88 adc b
89 adc c
8a adc d
8b adc e
8c adc h
8d adc l
8e adc m
8f adc a
90 sub b
91 sub c
92 sub d
93 sub e
94 sub h
95 sub l
96 sub m
97 sub a
98 sbb b
99 sbb c
9a sbb d
9b sbb e
9c sbb h
9d sbb l
9e sbb m
9f sbb a
a0 ana b
a1 ana c
a2 ana d
a3 ana e
a4 ana h
a5 ana l
a6 ana m
a7 ana a
a8 xra b
a9 xra c
aa xra d
ab xra e
ac xra h
ad xra l
ae xra m
af xra a
b0 ora b
b1 ora c
b2 ora d
b3 ora e
b4 ora h
b5 ora l
b6 ora m
b7 ora a
b8 cmp b
b9 cmp c
ba cmp d
bb cmp e
bc cmp h
bd cmp l
be cmp m
bf cmp a
c0 rnz
c1 pop b
c20000 jnz 0x0000
c30000 jmp 0x0000
c40000 cnz 0x0000
c5 push b
c600 adi 0x00
c7 rst 0x0000
c8 rz
c9 ret
ca0000 jz 0x0000
cb0000 xjmp 0xcb, 0x0000
cc0000 cz 0x0000
cd0000 call 0x0000
ce00 aci 0x00
cf rst 0x0008
d0 rnc
d1 pop d
d20000 jnc 0x0000
d300 out 0x00
d40000 cnc 0x0000
d5 push d
d600 sui 0x00
d7 rst 0x0010
d8 rc
d9 xret 0xd9
da0000 jc 0x0000
db00 in 0x00
dc0000 cc 0x0000
dd0000 xcall 0xdd, 0x0000
de00 sbi 0x00
df rst 0x0018
e0 rpo
e1 pop h
e20000 jpo 0x0000
e3 xthl
e40000 cpo 0x0000
e5 push h
e600 ani 0x00
e7 rst 0x0020
e8 rpe
e9 pchl
ea0000 jpe 0x0000
eb xchg
ec0000 cpe 0x0000
ed0000 xcall 0xed, 0x0000
ee00 xri 0x00
ef rst 0x0028
f0 rp
f1 pop psw
f20000 jp 0x0000
f3 di
f40000 cp 0x0000
f5 push psw
f600 ori 0x00
f7 rst 0x0030
f8 rm
f9 sphl
fa0000 jm 0x0000
fb ei
fc0000 cm 0x0000
fd0000 xcall 0xfd, 0x0000
fe00 cpi 0x00
ff rst 0x0038
