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INFO-DIR-SECTION Programming
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* gccint: (gccint).            Internals of the GNU Compiler Collection.
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   This file documents the internals of the GNU compilers.

   Published by the Free Software Foundation
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File: gccint.info,  Node: Condition Code,  Next: Costs,  Prev: Addressing Modes,  Up: Target Macros

Condition Code Status
=====================

   This describes the condition code status.

   The file `conditions.h' defines a variable `cc_status' to describe
how the condition code was computed (in case the interpretation of the
condition code depends on the instruction that it was set by).  This
variable contains the RTL expressions on which the condition code is
currently based, and several standard flags.

   Sometimes additional machine-specific flags must be defined in the
machine description header file.  It can also add additional
machine-specific information by defining `CC_STATUS_MDEP'.

 - Macro: CC_STATUS_MDEP
     C code for a data type which is used for declaring the `mdep'
     component of `cc_status'.  It defaults to `int'.

     This macro is not used on machines that do not use `cc0'.

 - Macro: CC_STATUS_MDEP_INIT
     A C expression to initialize the `mdep' field to "empty".  The
     default definition does nothing, since most machines don't use the
     field anyway.  If you want to use the field, you should probably
     define this macro to initialize it.

     This macro is not used on machines that do not use `cc0'.

 - Macro: NOTICE_UPDATE_CC (EXP, INSN)
     A C compound statement to set the components of `cc_status'
     appropriately for an insn INSN whose body is EXP.  It is this
     macro's responsibility to recognize insns that set the condition
     code as a byproduct of other activity as well as those that
     explicitly set `(cc0)'.

     This macro is not used on machines that do not use `cc0'.

     If there are insns that do not set the condition code but do alter
     other machine registers, this macro must check to see whether they
     invalidate the expressions that the condition code is recorded as
     reflecting.  For example, on the 68000, insns that store in address
     registers do not set the condition code, which means that usually
     `NOTICE_UPDATE_CC' can leave `cc_status' unaltered for such insns.
     But suppose that the previous insn set the condition code based
     on location `a4@(102)' and the current insn stores a new value in
     `a4'.  Although the condition code is not changed by this, it will
     no longer be true that it reflects the contents of `a4@(102)'.
     Therefore, `NOTICE_UPDATE_CC' must alter `cc_status' in this case
     to say that nothing is known about the condition code value.

     The definition of `NOTICE_UPDATE_CC' must be prepared to deal with
     the results of peephole optimization: insns whose patterns are
     `parallel' RTXs containing various `reg', `mem' or constants which
     are just the operands.  The RTL structure of these insns is not
     sufficient to indicate what the insns actually do.  What
     `NOTICE_UPDATE_CC' should do when it sees one is just to run
     `CC_STATUS_INIT'.

     A possible definition of `NOTICE_UPDATE_CC' is to call a function
     that looks at an attribute (*note Insn Attributes::) named, for
     example, `cc'.  This avoids having detailed information about
     patterns in two places, the `md' file and in `NOTICE_UPDATE_CC'.

 - Macro: EXTRA_CC_MODES
     Condition codes are represented in registers by machine modes of
     class `MODE_CC'.  By default, there is just one mode, `CCmode',
     with this class.  If you need more such modes, create a file named
     `MACHINE-modes.def' in your `config/MACHINE' directory (*note
     Anatomy of a Target Back End: Back End.), containing a list of
     these modes.  Each entry in the list should be a call to the macro
     `CC'.  This macro takes one argument, which is the name of the
     mode: it should begin with `CC'.  Do not put quotation marks
     around the name, or include the trailing `mode'; these are
     automatically added.  There should not be anything else in the file
     except comments.

     A sample `MACHINE-modes.def' file might look like this:

          CC (CC_NOOV)   /* Comparison only valid if there was no overflow. */
          CC (CCFP)      /* Floating point comparison that cannot trap. */
          CC (CCFPE)     /* Floating point comparison that may trap. */

     When you create this file, the macro `EXTRA_CC_MODES' is
     automatically defined by `configure', with value `1'.

 - Macro: SELECT_CC_MODE (OP, X, Y)
     Returns a mode from class `MODE_CC' to be used when comparison
     operation code OP is applied to rtx X and Y.  For example, on the
     SPARC, `SELECT_CC_MODE' is defined as (see *note Jump Patterns::
     for a description of the reason for this definition)

          #define SELECT_CC_MODE(OP,X,Y) \
            (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT          \
             ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode)    \
             : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS    \
                 || GET_CODE (X) == NEG) \
                ? CC_NOOVmode : CCmode))

     You need not define this macro if `EXTRA_CC_MODES' is not defined.

 - Macro: CANONICALIZE_COMPARISON (CODE, OP0, OP1)
     On some machines not all possible comparisons are defined, but you
     can convert an invalid comparison into a valid one.  For example,
     the Alpha does not have a `GT' comparison, but you can use an `LT'
     comparison instead and swap the order of the operands.

     On such machines, define this macro to be a C statement to do any
     required conversions.  CODE is the initial comparison code and OP0
     and OP1 are the left and right operands of the comparison,
     respectively.  You should modify CODE, OP0, and OP1 as required.

     GCC will not assume that the comparison resulting from this macro
     is valid but will see if the resulting insn matches a pattern in
     the `md' file.

     You need not define this macro if it would never change the
     comparison code or operands.

 - Macro: REVERSIBLE_CC_MODE (MODE)
     A C expression whose value is one if it is always safe to reverse a
     comparison whose mode is MODE.  If `SELECT_CC_MODE' can ever
     return MODE for a floating-point inequality comparison, then
     `REVERSIBLE_CC_MODE (MODE)' must be zero.

     You need not define this macro if it would always returns zero or
     if the floating-point format is anything other than
     `IEEE_FLOAT_FORMAT'.  For example, here is the definition used on
     the SPARC, where floating-point inequality comparisons are always
     given `CCFPEmode':

          #define REVERSIBLE_CC_MODE(MODE)  ((MODE) != CCFPEmode)

 - Macro: REVERSE_CONDITION (CODE, MODE)
     A C expression whose value is reversed condition code of the CODE
     for comparison done in CC_MODE MODE.  The macro is used only in
     case `REVERSIBLE_CC_MODE (MODE)' is nonzero.  Define this macro in
     case machine has some non-standard way how to reverse certain
     conditionals.  For instance in case all floating point conditions
     are non-trapping, compiler may freely convert unordered compares
     to ordered one.  Then definition may look like:

          #define REVERSE_CONDITION(CODE, MODE) \
             ((MODE) != CCFPmode ? reverse_condition (CODE) \
              : reverse_condition_maybe_unordered (CODE))

 - Macro: REVERSE_CONDEXEC_PREDICATES_P (CODE1, CODE2)
     A C expression that returns true if the conditional execution
     predicate CODE1 is the inverse of CODE2 and vice versa.  Define
     this to return 0 if the target has conditional execution
     predicates that cannot be reversed safely.  If no expansion is
     specified, this macro is defined as follows:

          #define REVERSE_CONDEXEC_PREDICATES_P (x, y) \
             ((x) == reverse_condition (y))


File: gccint.info,  Node: Costs,  Next: Scheduling,  Prev: Condition Code,  Up: Target Macros

Describing Relative Costs of Operations
=======================================

   These macros let you describe the relative speed of various
operations on the target machine.

 - Macro: REGISTER_MOVE_COST (MODE, FROM, TO)
     A C expression for the cost of moving data of mode MODE from a
     register in class FROM to one in class TO.  The classes are
     expressed using the enumeration values such as `GENERAL_REGS'.  A
     value of 2 is the default; other values are interpreted relative to
     that.

     It is not required that the cost always equal 2 when FROM is the
     same as TO; on some machines it is expensive to move between
     registers if they are not general registers.

     If reload sees an insn consisting of a single `set' between two
     hard registers, and if `REGISTER_MOVE_COST' applied to their
     classes returns a value of 2, reload does not check to ensure that
     the constraints of the insn are met.  Setting a cost of other than
     2 will allow reload to verify that the constraints are met.  You
     should do this if the `movM' pattern's constraints do not allow
     such copying.

 - Macro: MEMORY_MOVE_COST (MODE, CLASS, IN)
     A C expression for the cost of moving data of mode MODE between a
     register of class CLASS and memory; IN is zero if the value is to
     be written to memory, nonzero if it is to be read in.  This cost
     is relative to those in `REGISTER_MOVE_COST'.  If moving between
     registers and memory is more expensive than between two registers,
     you should define this macro to express the relative cost.

     If you do not define this macro, GCC uses a default cost of 4 plus
     the cost of copying via a secondary reload register, if one is
     needed.  If your machine requires a secondary reload register to
     copy between memory and a register of CLASS but the reload
     mechanism is more complex than copying via an intermediate, define
     this macro to reflect the actual cost of the move.

     GCC defines the function `memory_move_secondary_cost' if secondary
     reloads are needed.  It computes the costs due to copying via a
     secondary register.  If your machine copies from memory using a
     secondary register in the conventional way but the default base
     value of 4 is not correct for your machine, define this macro to
     add some other value to the result of that function.  The
     arguments to that function are the same as to this macro.

 - Macro: BRANCH_COST
     A C expression for the cost of a branch instruction.  A value of 1
     is the default; other values are interpreted relative to that.

   Here are additional macros which do not specify precise relative
costs, but only that certain actions are more expensive than GCC would
ordinarily expect.

 - Macro: SLOW_BYTE_ACCESS
     Define this macro as a C expression which is nonzero if accessing
     less than a word of memory (i.e. a `char' or a `short') is no
     faster than accessing a word of memory, i.e., if such access
     require more than one instruction or if there is no difference in
     cost between byte and (aligned) word loads.

     When this macro is not defined, the compiler will access a field by
     finding the smallest containing object; when it is defined, a
     fullword load will be used if alignment permits.  Unless bytes
     accesses are faster than word accesses, using word accesses is
     preferable since it may eliminate subsequent memory access if
     subsequent accesses occur to other fields in the same word of the
     structure, but to different bytes.

 - Macro: SLOW_UNALIGNED_ACCESS (MODE, ALIGNMENT)
     Define this macro to be the value 1 if memory accesses described
     by the MODE and ALIGNMENT parameters have a cost many times greater
     than aligned accesses, for example if they are emulated in a trap
     handler.

     When this macro is nonzero, the compiler will act as if
     `STRICT_ALIGNMENT' were nonzero when generating code for block
     moves.  This can cause significantly more instructions to be
     produced.  Therefore, do not set this macro nonzero if unaligned
     accesses only add a cycle or two to the time for a memory access.

     If the value of this macro is always zero, it need not be defined.
     If this macro is defined, it should produce a nonzero value when
     `STRICT_ALIGNMENT' is nonzero.

 - Macro: MOVE_RATIO
     The threshold of number of scalar memory-to-memory move insns,
     _below_ which a sequence of insns should be generated instead of a
     string move insn or a library call.  Increasing the value will
     always make code faster, but eventually incurs high cost in
     increased code size.

     Note that on machines where the corresponding move insn is a
     `define_expand' that emits a sequence of insns, this macro counts
     the number of such sequences.

     If you don't define this, a reasonable default is used.

 - Macro: MOVE_BY_PIECES_P (SIZE, ALIGNMENT)
     A C expression used to determine whether `move_by_pieces' will be
     used to copy a chunk of memory, or whether some other block move
     mechanism will be used.  Defaults to 1 if `move_by_pieces_ninsns'
     returns less than `MOVE_RATIO'.

 - Macro: MOVE_MAX_PIECES
     A C expression used by `move_by_pieces' to determine the largest
     unit a load or store used to copy memory is.  Defaults to
     `MOVE_MAX'.

 - Macro: CLEAR_RATIO
     The threshold of number of scalar move insns, _below_ which a
     sequence of insns should be generated to clear memory instead of a
     string clear insn or a library call.  Increasing the value will
     always make code faster, but eventually incurs high cost in
     increased code size.

     If you don't define this, a reasonable default is used.

 - Macro: CLEAR_BY_PIECES_P (SIZE, ALIGNMENT)
     A C expression used to determine whether `clear_by_pieces' will be
     used to clear a chunk of memory, or whether some other block clear
     mechanism will be used.  Defaults to 1 if `move_by_pieces_ninsns'
     returns less than `CLEAR_RATIO'.

 - Macro: STORE_BY_PIECES_P (SIZE, ALIGNMENT)
     A C expression used to determine whether `store_by_pieces' will be
     used to set a chunk of memory to a constant value, or whether some
     other mechanism will be used.  Used by `__builtin_memset' when
     storing values other than constant zero and by `__builtin_strcpy'
     when when called with a constant source string.  Defaults to
     `MOVE_BY_PIECES_P'.

 - Macro: USE_LOAD_POST_INCREMENT (MODE)
     A C expression used to determine whether a load postincrement is a
     good thing to use for a given mode.  Defaults to the value of
     `HAVE_POST_INCREMENT'.

 - Macro: USE_LOAD_POST_DECREMENT (MODE)
     A C expression used to determine whether a load postdecrement is a
     good thing to use for a given mode.  Defaults to the value of
     `HAVE_POST_DECREMENT'.

 - Macro: USE_LOAD_PRE_INCREMENT (MODE)
     A C expression used to determine whether a load preincrement is a
     good thing to use for a given mode.  Defaults to the value of
     `HAVE_PRE_INCREMENT'.

 - Macro: USE_LOAD_PRE_DECREMENT (MODE)
     A C expression used to determine whether a load predecrement is a
     good thing to use for a given mode.  Defaults to the value of
     `HAVE_PRE_DECREMENT'.

 - Macro: USE_STORE_POST_INCREMENT (MODE)
     A C expression used to determine whether a store postincrement is
     a good thing to use for a given mode.  Defaults to the value of
     `HAVE_POST_INCREMENT'.

 - Macro: USE_STORE_POST_DECREMENT (MODE)
     A C expression used to determine whether a store postdecrement is
     a good thing to use for a given mode.  Defaults to the value of
     `HAVE_POST_DECREMENT'.

 - Macro: USE_STORE_PRE_INCREMENT (MODE)
     This macro is used to determine whether a store preincrement is a
     good thing to use for a given mode.  Defaults to the value of
     `HAVE_PRE_INCREMENT'.

 - Macro: USE_STORE_PRE_DECREMENT (MODE)
     This macro is used to determine whether a store predecrement is a
     good thing to use for a given mode.  Defaults to the value of
     `HAVE_PRE_DECREMENT'.

 - Macro: NO_FUNCTION_CSE
     Define this macro if it is as good or better to call a constant
     function address than to call an address kept in a register.

 - Macro: NO_RECURSIVE_FUNCTION_CSE
     Define this macro if it is as good or better for a function to call
     itself with an explicit address than to call an address kept in a
     register.

 - Macro: RANGE_TEST_NON_SHORT_CIRCUIT
     Define this macro if a non-short-circuit operation produced by
     `fold_range_test ()' is optimal.  This macro defaults to true if
     `BRANCH_COST' is greater than or equal to the value 2.

 - Target Hook: bool TARGET_RTX_COSTS (rtx X, int CODE, int OUTER_CODE,
          int *TOTAL)
     This target hook describes the relative costs of RTL expressions.

     The cost may depend on the precise form of the expression, which is
     available for examination in X, and the rtx code of the expression
     in which it is contained, found in OUTER_CODE.  CODE is the
     expression code--redundant, since it can be obtained with
     `GET_CODE (X)'.

     In implementing this hook, you can use the construct
     `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.

     On entry to the hook, `*TOTAL' contains a default estimate for the
     cost of the expression.  The hook should modify this value as
     necessary.

     The hook returns true when all subexpressions of X have been
     processed, and false when `rtx_cost' should recurse.

 - Target Hook: int TARGET_ADDRESS_COST (rtx ADDRESS)
     This hook computes the cost of an addressing mode that contains
     ADDRESS.  If not defined, the cost is computed from the ADDRESS
     expression and the `TARGET_RTX_COST' hook.

     For most CISC machines, the default cost is a good approximation
     of the true cost of the addressing mode.  However, on RISC
     machines, all instructions normally have the same length and
     execution time.  Hence all addresses will have equal costs.

     In cases where more than one form of an address is known, the form
     with the lowest cost will be used.  If multiple forms have the
     same, lowest, cost, the one that is the most complex will be used.

     For example, suppose an address that is equal to the sum of a
     register and a constant is used twice in the same basic block.
     When this macro is not defined, the address will be computed in a
     register and memory references will be indirect through that
     register.  On machines where the cost of the addressing mode
     containing the sum is no higher than that of a simple indirect
     reference, this will produce an additional instruction and
     possibly require an additional register.  Proper specification of
     this macro eliminates this overhead for such machines.

     This hook is never called with an invalid address.

     On machines where an address involving more than one register is as
     cheap as an address computation involving only one register,
     defining `TARGET_ADDRESS_COST' to reflect this can cause two
     registers to be live over a region of code where only one would
     have been if `TARGET_ADDRESS_COST' were not defined in that
     manner.  This effect should be considered in the definition of
     this macro.  Equivalent costs should probably only be given to
     addresses with different numbers of registers on machines with
     lots of registers.


File: gccint.info,  Node: Scheduling,  Next: Sections,  Prev: Costs,  Up: Target Macros

Adjusting the Instruction Scheduler
===================================

   The instruction scheduler may need a fair amount of machine-specific
adjustment in order to produce good code.  GCC provides several target
hooks for this purpose.  It is usually enough to define just a few of
them: try the first ones in this list first.

 - Target Hook: int TARGET_SCHED_ISSUE_RATE (void)
     This hook returns the maximum number of instructions that can ever
     issue at the same time on the target machine.  The default is one.
     Although the insn scheduler can define itself the possibility of
     issue an insn on the same cycle, the value can serve as an
     additional constraint to issue insns on the same simulated
     processor cycle (see hooks `TARGET_SCHED_REORDER' and
     `TARGET_SCHED_REORDER2').  This value must be constant over the
     entire compilation.  If you need it to vary depending on what the
     instructions are, you must use `TARGET_SCHED_VARIABLE_ISSUE'.

     For the automaton based pipeline interface, you could define this
     hook to return the value of the macro `MAX_DFA_ISSUE_RATE'.

 - Target Hook: int TARGET_SCHED_VARIABLE_ISSUE (FILE *FILE, int
          VERBOSE, rtx INSN, int MORE)
     This hook is executed by the scheduler after it has scheduled an
     insn from the ready list.  It should return the number of insns
     which can still be issued in the current cycle.  The default is
     `MORE - 1' for insns other than `CLOBBER' and `USE', which
     normally are not counted against the issue rate.  You should
     define this hook if some insns take more machine resources than
     others, so that fewer insns can follow them in the same cycle.
     FILE is either a null pointer, or a stdio stream to write any
     debug output to.  VERBOSE is the verbose level provided by
     `-fsched-verbose-N'.  INSN is the instruction that was scheduled.

 - Target Hook: int TARGET_SCHED_ADJUST_COST (rtx INSN, rtx LINK, rtx
          DEP_INSN, int COST)
     This function corrects the value of COST based on the relationship
     between INSN and DEP_INSN through the dependence LINK.  It should
     return the new value.  The default is to make no adjustment to
     COST.  This can be used for example to specify to the scheduler
     using the traditional pipeline description that an output- or
     anti-dependence does not incur the same cost as a data-dependence.
     If the scheduler using the automaton based pipeline description,
     the cost of anti-dependence is zero and the cost of
     output-dependence is maximum of one and the difference of latency
     times of the first and the second insns.  If these values are not
     acceptable, you could use the hook to modify them too.  See also
     *note Automaton pipeline description::.

 - Target Hook: int TARGET_SCHED_ADJUST_PRIORITY (rtx INSN, int
          PRIORITY)
     This hook adjusts the integer scheduling priority PRIORITY of
     INSN.  It should return the new priority.  Reduce the priority to
     execute INSN earlier, increase the priority to execute INSN later.
     Do not define this hook if you do not need to adjust the
     scheduling priorities of insns.

 - Target Hook: int TARGET_SCHED_REORDER (FILE *FILE, int VERBOSE, rtx
          *READY, int *N_READYP, int CLOCK)
     This hook is executed by the scheduler after it has scheduled the
     ready list, to allow the machine description to reorder it (for
     example to combine two small instructions together on `VLIW'
     machines).  FILE is either a null pointer, or a stdio stream to
     write any debug output to.  VERBOSE is the verbose level provided
     by `-fsched-verbose-N'.  READY is a pointer to the ready list of
     instructions that are ready to be scheduled.  N_READYP is a
     pointer to the number of elements in the ready list.  The scheduler
     reads the ready list in reverse order, starting with
     READY[*N_READYP-1] and going to READY[0].  CLOCK is the timer tick
     of the scheduler.  You may modify the ready list and the number of
     ready insns.  The return value is the number of insns that can
     issue this cycle; normally this is just `issue_rate'.  See also
     `TARGET_SCHED_REORDER2'.

 - Target Hook: int TARGET_SCHED_REORDER2 (FILE *FILE, int VERBOSE, rtx
          *READY, int *N_READY, CLOCK)
     Like `TARGET_SCHED_REORDER', but called at a different time.  That
     function is called whenever the scheduler starts a new cycle.
     This one is called once per iteration over a cycle, immediately
     after `TARGET_SCHED_VARIABLE_ISSUE'; it can reorder the ready list
     and return the number of insns to be scheduled in the same cycle.
     Defining this hook can be useful if there are frequent situations
     where scheduling one insn causes other insns to become ready in
     the same cycle.  These other insns can then be taken into account
     properly.

 - Target Hook: void TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK (rtx
          HEAD, rtx TAIL)
     This hook is called after evaluation forward dependencies of insns
     in chain given by two parameter values (HEAD and TAIL
     correspondingly) but before insns scheduling of the insn chain.
     For example, it can be used for better insn classification if it
     requires analysis of dependencies.  This hook can use backward and
     forward dependencies of the insn scheduler because they are already
     calculated.

 - Target Hook: void TARGET_SCHED_INIT (FILE *FILE, int VERBOSE, int
          MAX_READY)
     This hook is executed by the scheduler at the beginning of each
     block of instructions that are to be scheduled.  FILE is either a
     null pointer, or a stdio stream to write any debug output to.
     VERBOSE is the verbose level provided by `-fsched-verbose-N'.
     MAX_READY is the maximum number of insns in the current scheduling
     region that can be live at the same time.  This can be used to
     allocate scratch space if it is needed, e.g. by
     `TARGET_SCHED_REORDER'.

 - Target Hook: void TARGET_SCHED_FINISH (FILE *FILE, int VERBOSE)
     This hook is executed by the scheduler at the end of each block of
     instructions that are to be scheduled.  It can be used to perform
     cleanup of any actions done by the other scheduling hooks.  FILE
     is either a null pointer, or a stdio stream to write any debug
     output to.  VERBOSE is the verbose level provided by
     `-fsched-verbose-N'.

 - Target Hook: int TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE (void)
     This hook is called many times during insn scheduling.  If the hook
     returns nonzero, the automaton based pipeline description is used
     for insn scheduling.  Otherwise the traditional pipeline
     description is used.  The default is usage of the traditional
     pipeline description.

     You should also remember that to simplify the insn scheduler
     sources an empty traditional pipeline description interface is
     generated even if there is no a traditional pipeline description
     in the `.md' file.  The same is true for the automaton based
     pipeline description.  That means that you should be accurate in
     defining the hook.

 - Target Hook: int TARGET_SCHED_DFA_PRE_CYCLE_INSN (void)
     The hook returns an RTL insn.  The automaton state used in the
     pipeline hazard recognizer is changed as if the insn were scheduled
     when the new simulated processor cycle starts.  Usage of the hook
     may simplify the automaton pipeline description for some VLIW
     processors.  If the hook is defined, it is used only for the
     automaton based pipeline description.  The default is not to
     change the state when the new simulated processor cycle starts.

 - Target Hook: void TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN (void)
     The hook can be used to initialize data used by the previous hook.

 - Target Hook: int TARGET_SCHED_DFA_POST_CYCLE_INSN (void)
     The hook is analogous to `TARGET_SCHED_DFA_PRE_CYCLE_INSN' but used
     to changed the state as if the insn were scheduled when the new
     simulated processor cycle finishes.

 - Target Hook: void TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN (void)
     The hook is analogous to `TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN' but
     used to initialize data used by the previous hook.

 - Target Hook: int TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
          (void)
     This hook controls better choosing an insn from the ready insn
     queue for the DFA-based insn scheduler.  Usually the scheduler
     chooses the first insn from the queue.  If the hook returns a
     positive value, an additional scheduler code tries all
     permutations of `TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
     ()' subsequent ready insns to choose an insn whose issue will
     result in maximal number of issued insns on the same cycle.  For
     the VLIW processor, the code could actually solve the problem of
     packing simple insns into the VLIW insn.  Of course, if the rules
     of VLIW packing are described in the automaton.

     This code also could be used for superscalar RISC processors.  Let
     us consider a superscalar RISC processor with 3 pipelines.  Some
     insns can be executed in pipelines A or B, some insns can be
     executed only in pipelines B or C, and one insn can be executed in
     pipeline B.  The processor may issue the 1st insn into A and the
     2nd one into B.  In this case, the 3rd insn will wait for freeing B
     until the next cycle.  If the scheduler issues the 3rd insn the
     first, the processor could issue all 3 insns per cycle.

     Actually this code demonstrates advantages of the automaton based
     pipeline hazard recognizer.  We try quickly and easy many insn
     schedules to choose the best one.

     The default is no multipass scheduling.

 - Target Hook: int
TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD (rtx)
     This hook controls what insns from the ready insn queue will be
     considered for the multipass insn scheduling.  If the hook returns
     zero for insn passed as the parameter, the insn will be not chosen
     to be issued.

     The default is that any ready insns can be chosen to be issued.

 - Target Hook: int TARGET_SCHED_DFA_NEW_CYCLE (FILE *, int, rtx, int,
          int, int *)
     This hook is called by the insn scheduler before issuing insn
     passed as the third parameter on given cycle.  If the hook returns
     nonzero, the insn is not issued on given processors cycle.
     Instead of that, the processor cycle is advanced.  If the value
     passed through the last parameter is zero, the insn ready queue is
     not sorted on the new cycle start as usually.  The first parameter
     passes file for debugging output.  The second one passes the
     scheduler verbose level of the debugging output.  The forth and
     the fifth parameter values are correspondingly processor cycle on
     which the previous insn has been issued and the current processor
     cycle.

 - Target Hook: void TARGET_SCHED_INIT_DFA_BUBBLES (void)
     The DFA-based scheduler could take the insertion of nop operations
     for better insn scheduling into account.  It can be done only if
     the multi-pass insn scheduling works (see hook
     `TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD').

     Let us consider a VLIW processor insn with 3 slots.  Each insn can
     be placed only in one of the three slots.  We have 3 ready insns
     A, B, and C.  A and C can be placed only in the 1st slot, B can be
     placed only in the 3rd slot.  We described the automaton which
     does not permit empty slot gaps between insns (usually such
     description is simpler).  Without this code the scheduler would
     place each insn in 3 separate VLIW insns.  If the scheduler places
     a nop insn into the 2nd slot, it could place the 3 insns into 2
     VLIW insns.  What is the nop insn is returned by hook
     `TARGET_SCHED_DFA_BUBBLE'.  Hook `TARGET_SCHED_INIT_DFA_BUBBLES'
     can be used to initialize or create the nop insns.

     You should remember that the scheduler does not insert the nop
     insns.  It is not wise because of the following optimizations.
     The scheduler only considers such possibility to improve the
     result schedule.  The nop insns should be inserted lately, e.g. on
     the final phase.

 - Target Hook: rtx TARGET_SCHED_DFA_BUBBLE (int INDEX)
     This hook `FIRST_CYCLE_MULTIPASS_SCHEDULING' is used to insert nop
     operations for better insn scheduling when DFA-based scheduler
     makes multipass insn scheduling (see also description of hook
     `TARGET_SCHED_INIT_DFA_BUBBLES').  This hook returns a nop insn
     with given INDEX.  The indexes start with zero.  The hook should
     return `NULL' if there are no more nop insns with indexes greater
     than given index.

   Macros in the following table are generated by the program `genattr'
and can be useful for writing the hooks.

 - Macro: TRADITIONAL_PIPELINE_INTERFACE
     The macro definition is generated if there is a traditional
     pipeline description in `.md' file. You should also remember that
     to simplify the insn scheduler sources an empty traditional
     pipeline description interface is generated even if there is no a
     traditional pipeline description in the `.md' file.  The macro can
     be used to distinguish the two types of the traditional interface.

 - Macro: DFA_PIPELINE_INTERFACE
     The macro definition is generated if there is an automaton pipeline
     description in `.md' file.  You should also remember that to
     simplify the insn scheduler sources an empty automaton pipeline
     description interface is generated even if there is no an automaton
     pipeline description in the `.md' file.  The macro can be used to
     distinguish the two types of the automaton interface.

 - Macro: MAX_DFA_ISSUE_RATE
     The macro definition is generated in the automaton based pipeline
     description interface.  Its value is calculated from the automaton
     based pipeline description and is equal to maximal number of all
     insns described in constructions `define_insn_reservation' which
     can be issued on the same processor cycle.


File: gccint.info,  Node: Sections,  Next: PIC,  Prev: Scheduling,  Up: Target Macros

Dividing the Output into Sections (Texts, Data, ...)
====================================================

   An object file is divided into sections containing different types of
data.  In the most common case, there are three sections: the "text
section", which holds instructions and read-only data; the "data
section", which holds initialized writable data; and the "bss section",
which holds uninitialized data.  Some systems have other kinds of
sections.

   The compiler must tell the assembler when to switch sections.  These
macros control what commands to output to tell the assembler this.  You
can also define additional sections.

 - Macro: TEXT_SECTION_ASM_OP
     A C expression whose value is a string, including spacing,
     containing the assembler operation that should precede
     instructions and read-only data.  Normally `"\t.text"' is right.

 - Macro: TEXT_SECTION
     A C statement that switches to the default section containing
     instructions.  Normally this is not needed, as simply defining
     `TEXT_SECTION_ASM_OP' is enough.  The MIPS port uses this to sort
     all functions after all data declarations.

 - Macro: HOT_TEXT_SECTION_NAME
     If defined, a C string constant for the name of the section
     containing most frequently executed functions of the program.  If
     not defined, GCC will provide a default definition if the target
     supports named sections.

 - Macro: UNLIKELY_EXECUTED_TEXT_SECTION_NAME
     If defined, a C string constant for the name of the section
     containing unlikely executed functions in the program.

 - Macro: DATA_SECTION_ASM_OP
     A C expression whose value is a string, including spacing,
     containing the assembler operation to identify the following data
     as writable initialized data.  Normally `"\t.data"' is right.

 - Macro: READONLY_DATA_SECTION_ASM_OP
     A C expression whose value is a string, including spacing,
     containing the assembler operation to identify the following data
     as read-only initialized data.

 - Macro: READONLY_DATA_SECTION
     A macro naming a function to call to switch to the proper section
     for read-only data.  The default is to use
     `READONLY_DATA_SECTION_ASM_OP' if defined, else fall back to
     `text_section'.

     The most common definition will be `data_section', if the target
     does not have a special read-only data section, and does not put
     data in the text section.

 - Macro: SHARED_SECTION_ASM_OP
     If defined, a C expression whose value is a string, including
     spacing, containing the assembler operation to identify the
     following data as shared data.  If not defined,
     `DATA_SECTION_ASM_OP' will be used.

 - Macro: BSS_SECTION_ASM_OP
     If defined, a C expression whose value is a string, including
     spacing, containing the assembler operation to identify the
     following data as uninitialized global data.  If not defined, and
     neither `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
     uninitialized global data will be output in the data section if
     `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
     used.

 - Macro: SHARED_BSS_SECTION_ASM_OP
     If defined, a C expression whose value is a string, including
     spacing, containing the assembler operation to identify the
     following data as uninitialized global shared data.  If not
     defined, and `BSS_SECTION_ASM_OP' is, the latter will be used.

 - Macro: INIT_SECTION_ASM_OP
     If defined, a C expression whose value is a string, including
     spacing, containing the assembler operation to identify the
     following data as initialization code.  If not defined, GCC will
     assume such a section does not exist.

 - Macro: FINI_SECTION_ASM_OP
     If defined, a C expression whose value is a string, including
     spacing, containing the assembler operation to identify the
     following data as finalization code.  If not defined, GCC will
     assume such a section does not exist.

 - Macro: CRT_CALL_STATIC_FUNCTION (SECTION_OP, FUNCTION)
     If defined, an ASM statement that switches to a different section
     via SECTION_OP, calls FUNCTION, and switches back to the text
     section.  This is used in `crtstuff.c' if `INIT_SECTION_ASM_OP' or
     `FINI_SECTION_ASM_OP' to calls to initialization and finalization
     functions from the init and fini sections.  By default, this macro
     uses a simple function call.  Some ports need hand-crafted
     assembly code to avoid dependencies on registers initialized in
     the function prologue or to ensure that constant pools don't end
     up too far way in the text section.

 - Macro: FORCE_CODE_SECTION_ALIGN
     If defined, an ASM statement that aligns a code section to some
     arbitrary boundary.  This is used to force all fragments of the
     `.init' and `.fini' sections to have to same alignment and thus
     prevent the linker from having to add any padding.

 - Macro: EXTRA_SECTIONS
     A list of names for sections other than the standard two, which are
     `in_text' and `in_data'.  You need not define this macro on a
     system with no other sections (that GCC needs to use).

 - Macro: EXTRA_SECTION_FUNCTIONS
     One or more functions to be defined in `varasm.c'.  These
     functions should do jobs analogous to those of `text_section' and
     `data_section', for your additional sections.  Do not define this
     macro if you do not define `EXTRA_SECTIONS'.

 - Macro: JUMP_TABLES_IN_TEXT_SECTION
     Define this macro to be an expression with a nonzero value if jump
     tables (for `tablejump' insns) should be output in the text
     section, along with the assembler instructions.  Otherwise, the
     readonly data section is used.

     This macro is irrelevant if there is no separate readonly data
     section.

 - Target Hook: void TARGET_ASM_SELECT_SECTION (tree EXP, int RELOC,
          unsigned HOST_WIDE_INT ALIGN)
     Switches to the appropriate section for output of EXP.  You can
     assume that EXP is either a `VAR_DECL' node or a constant of some
     sort.  RELOC indicates whether the initial value of EXP requires
     link-time relocations.  Bit 0 is set when variable contains local
     relocations only, while bit 1 is set for global relocations.
     Select the section by calling `data_section' or one of the
     alternatives for other sections.  ALIGN is the constant alignment
     in bits.

     The default version of this function takes care of putting
     read-only variables in `readonly_data_section'.

 - Target Hook: void TARGET_ASM_UNIQUE_SECTION (tree DECL, int RELOC)
     Build up a unique section name, expressed as a `STRING_CST' node,
     and assign it to `DECL_SECTION_NAME (DECL)'.  As with
     `TARGET_ASM_SELECT_SECTION', RELOC indicates whether the initial
     value of EXP requires link-time relocations.

     The default version of this function appends the symbol name to the
     ELF section name that would normally be used for the symbol.  For
     example, the function `foo' would be placed in `.text.foo'.
     Whatever the actual target object format, this is often good
     enough.

 - Target Hook: void TARGET_ASM_SELECT_RTX_SECTION (enum machine_mode
          MODE, rtx X, unsigned HOST_WIDE_INT ALIGN)
     Switches to the appropriate section for output of constant pool
     entry X in MODE.  You can assume that X is some kind of constant
     in RTL.  The argument MODE is redundant except in the case of a
     `const_int' rtx.  Select the section by calling
     `readonly_data_section' or one of the alternatives for other
     sections.  ALIGN is the constant alignment in bits.

     The default version of this function takes care of putting symbolic
     constants in `flag_pic' mode in `data_section' and everything else
     in `readonly_data_section'.

 - Target Hook: void TARGET_ENCODE_SECTION_INFO (tree DECL, rtx RTL,
          int NEW_DECL_P)
     Define this hook if references to a symbol or a constant must be
     treated differently depending on something about the variable or
     function named by the symbol (such as what section it is in).

     The hook is executed immediately after rtl has been created for
     DECL, which may be a variable or function declaration or an entry
     in the constant pool.  In either case, RTL is the rtl in question.
     Do _not_ use `DECL_RTL (DECL)' in this hook; that field may not
     have been initialized yet.

     In the case of a constant, it is safe to assume that the rtl is a
     `mem' whose address is a `symbol_ref'.  Most decls will also have
     this form, but that is not guaranteed.  Global register variables,
     for instance, will have a `reg' for their rtl.  (Normally the
     right thing to do with such unusual rtl is leave it alone.)

     The NEW_DECL_P argument will be true if this is the first time
     that `TARGET_ENCODE_SECTION_INFO' has been invoked on this decl.
     It will be false for subsequent invocations, which will happen for
     duplicate declarations.  Whether or not anything must be done for
     the duplicate declaration depends on whether the hook examines
     `DECL_ATTRIBUTES'.  NEW_DECL_P is always true when the hook is
     called for a constant.

     The usual thing for this hook to do is to record flags in the
     `symbol_ref', using `SYMBOL_REF_FLAG' or `SYMBOL_REF_FLAGS'.
     Historically, the name string was modified if it was necessary to
     encode more than one bit of information, but this practice is now
     discouraged; use `SYMBOL_REF_FLAGS'.

     The default definition of this hook, `default_encode_section_info'
     in `varasm.c', sets a number of commonly-useful bits in
     `SYMBOL_REF_FLAGS'.  Check whether the default does what you need
     before overriding it.

 - Target Hook: const char *TARGET_STRIP_NAME_ENCODING (const char
          *name)
     Decode NAME and return the real name part, sans the characters
     that `TARGET_ENCODE_SECTION_INFO' may have added.

 - Target Hook: bool TARGET_IN_SMALL_DATA_P (tree EXP)
     Returns true if EXP should be placed into a "small data" section.
     The default version of this hook always returns false.

 - Variable: Target Hook bool TARGET_HAVE_SRODATA_SECTION
     Contains the value true if the target places read-only "small
     data" into a separate section.  The default value is false.

 - Target Hook: bool TARGET_BINDS_LOCAL_P (tree EXP)
     Returns true if EXP names an object for which name resolution
     rules must resolve to the current "module" (dynamic shared library
     or executable image).

     The default version of this hook implements the name resolution
     rules for ELF, which has a looser model of global name binding
     than other currently supported object file formats.

 - Variable: Target Hook bool TARGET_HAVE_TLS
     Contains the value true if the target supports thread-local
     storage.  The default value is false.


File: gccint.info,  Node: PIC,  Next: Assembler Format,  Prev: Sections,  Up: Target Macros

Position Independent Code
=========================

   This section describes macros that help implement generation of
position independent code.  Simply defining these macros is not enough
to generate valid PIC; you must also add support to the macros
`GO_IF_LEGITIMATE_ADDRESS' and `PRINT_OPERAND_ADDRESS', as well as
`LEGITIMIZE_ADDRESS'.  You must modify the definition of `movsi' to do
something appropriate when the source operand contains a symbolic
address.  You may also need to alter the handling of switch statements
so that they use relative addresses.

 - Macro: PIC_OFFSET_TABLE_REGNUM
     The register number of the register used to address a table of
     static data addresses in memory.  In some cases this register is
     defined by a processor's "application binary interface" (ABI).
     When this macro is defined, RTL is generated for this register
     once, as with the stack pointer and frame pointer registers.  If
     this macro is not defined, it is up to the machine-dependent files
     to allocate such a register (if necessary).  Note that this
     register must be fixed when in use (e.g.  when `flag_pic' is true).

 - Macro: PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
     Define this macro if the register defined by
     `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls.  Do not define
     this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined.

 - Macro: FINALIZE_PIC
     By generating position-independent code, when two different
     programs (A and B) share a common library (libC.a), the text of
     the library can be shared whether or not the library is linked at
     the same address for both programs.  In some of these
     environments, position-independent code requires not only the use
     of different addressing modes, but also special code to enable the
     use of these addressing modes.

     The `FINALIZE_PIC' macro serves as a hook to emit these special
     codes once the function is being compiled into assembly code, but
     not before.  (It is not done before, because in the case of
     compiling an inline function, it would lead to multiple PIC
     prologues being included in functions which used inline functions
     and were compiled to assembly language.)

 - Macro: LEGITIMATE_PIC_OPERAND_P (X)
     A C expression that is nonzero if X is a legitimate immediate
     operand on the target machine when generating position independent
     code.  You can assume that X satisfies `CONSTANT_P', so you need
     not check this.  You can also assume FLAG_PIC is true, so you need
     not check it either.  You need not define this macro if all
     constants (including `SYMBOL_REF') can be immediate operands when
     generating position independent code.


File: gccint.info,  Node: Assembler Format,  Next: Debugging Info,  Prev: PIC,  Up: Target Macros

Defining the Output Assembler Language
======================================

   This section describes macros whose principal purpose is to describe
how to write instructions in assembler language--rather than what the
instructions do.

* Menu:

* File Framework::       Structural information for the assembler file.
* Data Output::          Output of constants (numbers, strings, addresses).
* Uninitialized Data::   Output of uninitialized variables.
* Label Output::         Output and generation of labels.
* Initialization::       General principles of initialization
			   and termination routines.
* Macros for Initialization::
			 Specific macros that control the handling of
			   initialization and termination routines.
* Instruction Output::   Output of actual instructions.
* Dispatch Tables::      Output of jump tables.
* Exception Region Output:: Output of exception region code.
* Alignment Output::     Pseudo ops for alignment and skipping data.

