POWERPC_AS(1)

NAME
powerpc_as - assembler for PowerPC

SYNOPSIS
as [options] argument ...

DESCRIPTION
This assembler is made with the general framework described in uni_ass(6).

It can assemble the instructions from Book I and Book II of PowerPC version 2.01. This includes the branch, integer, and floating point instructions from Book I; and the cache, synchronization, and time base instructions from Book II.

There is no support for other instructions, such as supervisor-mode instructions or vector instructions. There is some support for 64-bit integer instructions, but the assembler only has 32-bit symbols.

SYNTAX

  general purpose registers
There are 32 GPRs from r0 to r31. In this assembler, sp is an alias for r1, and fp is an alias for r2, because ack uses r1 as the stack pointer and r2 as the frame pointer. Other compilers don't use r2 as the frame pointer.

GPR syntax requires a register name, not a number. For example, ‘addi r5, r4, 1’ works, but ‘addi 5, 4, 1’ is a syntax error.

Certain instructions ignore the contents of r0 and use zero. This happens when using r0 as the second operand of addi or addis, or when addressing ‘expr(r0)’ or ‘r0, gpr’. The syntax is still the name r0, not the number 0.

  floating point registers
There are 32 FPRs from f0 to f31. Each FPR has 64 bits and can hold a single-precision or double-precision number. FPR syntax requires a register name, not a number.

  special purpose registers
The three named SPRs are ctr (count register), lr (link register), and xer (exception register). ‘mfspr’ and ‘mtspr’ allow these names or a number.

  condition register
There is a 32-bit condition register, where bit 0 is most significant, and bit 31 is least significant. This gets split into 8 registers of 4 bits each, from cr0 (with bits 0 to 3) to cr7 (with bits 28 to 31). Some instructions use the names cr0 to cr7, others use a bit numbered 0 to 31, and others use all 32 bits.

  addressing modes
‘expr(gpr)’ addresses expr + the contents of gpr, except that ‘expr(r0)’ addresses expr + 0. A few instructions, like ‘stwu’, also update gpr by setting it to the address.

‘gprA, gprB’ in certain instructions addresses the contents of gprA + the contents of gprB, except that ‘r0, gprB’ addresses 0 + the contents of gprB.

  16-bit operands
Some instructions have a 16-bit operand. This can be a bare expr (which must fit signed or unsigned 16 bits), or it can be one of these special functions:

hi16[expr], ha16[expr]
    Returns the high half of the 32-bit value of the expression. If the low half is negative (from 0x8000 to 0xffff), then ha16[] adjusts the high half by adding 1. Use hi16[] if the instruction with lo16[] is going to interpret its operand as an unsigned value, or ha16[] if it will interpret it as signed.

    If expr is not absolute, then the assembler must generate a fixup for the linker. The fixup only works if the instruction is ‘addis gpr, r0, hx16[expr]’ or ‘lis gpr, hx16[expr]’.

lo16[expr]
    Returns the low half of the 32-bit value of the expression.

  short forms
Some instructions have short forms using extended mnemonics (or simplified mnemonics) like li, srwi, and many others.

li r6, 789
    is short for: addi r6, r0, 789

srwi r3, r4, 2
    is short for: rlwinm r3, r4, 30, 2, 31

This assembler doesn't support extended mnemonics with branch prediction, such as blt+ or bne-. It always parses ‘+’ and ‘-’ as operators, never as part of a mnemonic.

EXAMPLES
There are two ways to load r3 with _symbol = 0x1234abcd. One way is

   lis  r3, hi16[_symbol]
   ori  r3, r3, lo16[_symbol]  ! r3 = 0x12340000 | 0x0000abcd

The other way is

   lis  r3, ha16[_symbol]
   addi r3, r3, lo16[_symbol]  ! r3 = 0x12350000 + 0xffffabcd

The next code adds 1 to a global variable.

   lis  r3, ha16[_var]
   lwz  r4, lo16[_var](r3)
   addi r4, r4, 1
   stw  r4, lo16[_var](r3)

SEE ALSO
uni_ass(6), ack(1)

Freescale Semiconductor, Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3, September 2005.

IBM, PowerPC User Instruction Set Architecture, Book I, Version 2.01, September 2003.

IBM, PowerPC Virtual Environment Architecture, Book II, Version 2.01, December 2003.

CAVEATS
Beware that not every processor can run every instruction. The 32-bit processors can't run 64-bit instructions like lwa, std, and fctid. The PowerPC 601 can't run stfiwx, nor fres, frsqrte, fsel. Many models, like the PowerPC G4, can't run fsqrt nor fsqrts.