;*************** OPTI HiD/386 Chipset 82C382D/82C381 ***************
;*************** OPTI HiB/486 Chipset 82C482B/82C481 ***************
;*************** Dateiname: OPTI482.CFG              ***************

INDEXPORT=22H   ;OPTI-Adressen
DATENPORT=24H
;******************************************************************

INDEX=10H       ;Remap Address
;******************************************************************

BIT=765        ;Unused

BIT=4          ;0/1 Remap

BIT=3210       ;Address Range
                0000=no mapping
                0001=1 MB
                0010=2 MB
                0011=3 MB
                0100=4 MB
                0101=5 MB
                0110=6 MB
                0111=7 MB
                1000=8 MB
                1001=9 MB
                1010=10MB
                1011=11MB
                1100=12MB
                1101=13MB
                1110=14MB
                1111=15MB

INDEX=11H      ; Shadow RAM Register
;******************************************************************

BIT=7          ;ROM-Enable
                1= Read from ROM, Write to DRAM
                0= R/W on DRAM, DRAM is write protected

BIT=6          ;Shadow RAM at D000h-DFFFh
                0=Disable RAM, Access AT-BUS
                1=Enable  RAM  as specified by Register 12H

BIT=5          ;Shadow RAM at E000h-EFFFh
                0=Disable RAM, enable ROMCS on XD-Bus
                1=Enable  RAM  as specified by Register 12H

BIT=4          ;0/1 Shadow RAM at D000h-DFFFh Write Protection

BIT=3          ;0/1 Shadow RAM at E000h-EFFFh

BIT=2          ;1/0 RAS timeout Precharge Counter

BIT=10         ;unused


Index=12H      ;Memory Enable Register
;******************************************************************

BIT=7          ;0/1 Shadow RAM at EC00h-EFFFh

BIT=6          ;0/1 Shadow RAM at E800h-EBFFh

BIT=5          ;0/1 Shadow RAM at E400h-E7FFh

BIT=4          ;0/1 Shadow RAM at E000h-E3FFh

BIT=3          ;0/1 Shadow RAM at DC00h-DFFFh

BIT=2          ;0/1 Shadow RAM at D800h-DBFFh

BIT=1          ;0/1 Shadow RAM at D400h-D7FFh

BIT=0          ;0/1 Shadow RAM at D000h-D3FFh



INDEX=13H      ;Bank Configuration Register
;******************************************************************

BIT=7         ; Unused

BIT=654       ;DRAM Typ Bank 0/1
                000=B0:256K B1:-
                001=B0:256K B1:256K
                010=B0:256K B1:1M
                011=B0:1M   B1: 256K
                100=B0:1M   B1: -
                101=B0:1M   B1: 1M
                1xx=B0: -   B1: -

BIT=3          ;unused

BIT=210        ;DRAM Typ Bank 2/3
                000=B2:256K B3:-
                001=B2:256K B3:256K
                010=B2:256K B3:1M
                011=B2:1M   B3: 256K
                100=B2:1M   B3: -
                101=B2:1M   B2: 1M
                110=B2: -   B3: -
                111=B2:256K B3: -


Index=14H      ;DRAM Configuration Register
;******************************************************************

BIT=76         ;Additional Read Cycle Wait States
                00= 0
                01= 1 Waits
                10= 2 Waits
                11= 3 Waits
BIT=5         ;Additional Write Cycle Wait States
                0= 0 Waits
                1= 1 Waits

BIT=43210     ;unused

INDEX=15H      ; Region Shadow Register
;****************************************************************

BIT=7         ;  unused

BIT=6         ; Shadow RAM Copy enable for address area C0000h-EFFFFh
                0=Read/write at AT-Bus
                1=Read from AT-Bus, Write into  Shadow RAM

BIT=5         ;Shadow Write protect at address area C0000h-CFFFFh
               0=Disabled, RAM is r/w

               1=Enabled, RAM is ro

BIT=4         ;Shadow RAM at C0000h-CFFFFFh
              0=disable RAM
              1=Enable  RAM  as specified by BITs 3210

BIT=3         ;0/1 Shadow RAM at CC000h-CFFFFFh

BIT=2         ;0/1 Shadow RAM at C8000h-CBFFFFh

BIT=1         ;0/1 Shadow RAM at C4000h-C7FFFFh

BIT=0         ;0/1 Shadow RAM at C0000h-C3FFFFh


INDEX=16H     ; Fast Gate A20 Register
;****************************************************************

BIT=7654      ; Unused

BIT=3         ; Fast GateA20 Control
              0=GA20-Signal controlled by GATEA20-Signal
              1=CPUA20 is enabled onto GA20

BIT=210       ; Unused

INDEX=17H     ;Cache Configuration
;****************************************************************

BIT=7         ;Cache enable (via Signal NCA)
              0=Cache enable (if cacheable area)
              1=Cache disable

BIT=6         ;must be 1 (482), Cache (382)
              0=Cache Disabled (382)
              1=Cache Enabled  (382)

BIT=5        ; must be 1 (482), Write Thru (382)

BIT=43        ;Cache Control (482)/ Line Size (382)
              00= Disabled (482) / 4 Bytes (382)
              01= unused   (482) / 8 Bytes (382)
              10= Enable with Secondary Cache (482)/ 16 Bytes (382)
              11= Enable DRAM Burst with no Secondary Cache (482)

BIT=210      ; unused

INDEX=18H  ; Non-Cacheable Block Size 1 Register
;****************************************************************

BIT=765    ; Size of Non-cacheable Memory Block 1
            000=64K
            001=128K
            010=256K
            011=512K
            100=1M
            101=4M
            110=8M
            111=disabled

BIT=43210  ; Unused


INDEX=19H  ; Non-Cacheable Block Address 1 Register
;****************************************************************

BIT=76543210 ; A23--A16 Address-BITs of non Cacheable Memory Block 1

INDEX=1AH  ; Non-Cacheable Block Size 2 Register
;****************************************************************

BIT=765    ; Size of Non-cacheable Memory Block 2
            000=64K
            001=128K
            010=256K
            011=512K
            100=Reserved
            110=Reserved
            111=disabled

BIT=43210  ; Unused


INDEX=1BH  ; Non-Cacheable Block Address 1 Register
;****************************************************************

BIT=76543210 ; A23-A16 Address-BITs of non Cacheable Memory Block 2


INDEX=1CH   ; Cacheable Area Register
;****************************************************************

BIT=7654    ; Cacheable Address Range dor local memory
                0001=1 MB
                0010=2 MB
                0011=3 MB
                0100=4 MB
                0101=5 MB
                0110=6 MB
                0111=7 MB
                1000=8 MB
                1001=9 MB
                1010=10MB
                1011=11MB
                1100=12MB
                1101=13MB
                1110=14MB
                1111=15MB
                0000=16MB

BIT=3       ;   256 KB Remapped area Cacheable
            0= Non-Cacheable
            1= Cacheable

BIT=210     ; unused
