;**********************************************************
NAME=iNTEL ARIES PCIset
;**********************************************************
ConfigAccess=1
MACRO OPEN =0CFBh:xxxxxxx1,0CFAh:00000000
MACRO CLOSE=0CFBh:xxxxxxx0
MODE=INDEX32                       ;; alle Zugriffe 32-Bittig
INDEXPORT=0CF8h                    ;; CONFADDR
DATENPORT=0CFCh                    ;; CONFDATA
BASEADR=80002800h

*IF 0:<>$8086

 WRITELN "CONFIGAccess 1 nicht implementiert"
 MODE=DIRECT
 ConfigAccess=0
 MACRO OPEN=0CF8h:1111xxxx,0CFAh:00000000
 MACRO CLOSE=0CF8h:0000xxxx,0CFAh:00000000
 BASEADR=C000h

 *IF 0:<>$8086
   WRITELN "CONFIGAccess 0 nicht implementiert"
   EXIT "Abbruch, kein PCI-Zugriff m”glich"
 *ELSE
   WRITELN "CONFIGAccess 0 implementiert"
 *ENDIF
*ELSE
    WRITELN "CONFIGAccess 1 implementiert"
*ENDIF

;**********************************************************
CR0        ; Prozessor Controll Register 0
;**********************************************************
BIT=30,29   ; L1-Cache CD, NW
            00=Normal
            01=Invalid (=> Protection Exception)
            10=Cache freeze coherent
            11=Cache freeze incoherent
BIT=18     ;0/1 Alignment-Check
BIT=16     ;0/1 Write Protect

;**********************************************************
INDEX=40h  ;PCI Control Register
;**********************************************************

BIT=2	   ;0/1 PCI Posted Write Buffer Enable	 
BIT=1	   ;0/1 CPU-to-PCI Bursting Enable
BIT=0	   ;0/1 CPU-to-PCI Byte Merging

;**********************************************************
INDEX16=52h ;L2 Cache Control Register
;**********************************************************
BIT=12	   ;Hit Dirty Write Cycle Time
	    0=determined by Bit 11
	    1=0 Wait-State(2-1-1-1)
BIT=11	   ;Write Cycle Time
	    0=Timing for L2 cache writes :4-2-2-2
	    1=Timing for L2 cache writes :3-2-2-2
BIT=10,09  ;Subsequent Read Cache Timing
	    00=X-3-3-3
	    01=X-2-2-2
	    10=X-1-1-1
BIT=08	   ;Initial Read Timing
	    0= 3-x-x-x
	    1= 2-x-x-x
BIT=04      ;Cache Configuration
	    0= non-interleaved
	    1= interleaved
BIT=03      ;L2 Cache Write Policy
	    0= write-trough
	    1= write-back
BIT=02,01,00 ;L2 Cache Size
	    000= Disabled
	    001= 64 KBytes
	    010= 128 KBytes
	    011= 256 Kbytes
	    100= 512 Kbytes

;****************************************
INDEX16=56h
;****************************************
BIT=03      ;0/1 Fast Page Write Enable
BIT=02      ;0/1 Fast Page Data Read Enable
BIT=01      ;0/1 Fast Page Code Read Enable

;****************************************
INDEX16=48h
;****************************************
BIT=01,00   ;PCI IDE Enable
	     00= Disabled
	     01= Primary
             10= Secondary

;****************************************
INDEX=B2h   ;APM Control Port
;****************************************
BIT=76543210 ;APM 

;****************************************
INDEX=B3h   ;APM Status Port
;****************************************
BIT=76543210 ;APM Status

;****************************************
INDEX=70h   ;SMRAM Control Register
;****************************************
BIT=6       ;SMRAM Space Open
BIT=5	    ;SMRAM Close
BIT=4       ;SMRAM Lock
BIT=210     ;SMRAM Base Address (see Docu)

;****************************************
INDEX=A0h   ;SMI Control Register
;****************************************
BIT=43      ;Fast Off Timer Control
	     00= 1 Minute
             01= Disabled
             10= 1 HCLKIN
             11= 1 msec
BIT=2       ;0/1 Signal Throttle Enable
BIT=1       ;0/1 STPCLK Signal Enable
BIT=0       ;SMI Signal

;****************************************
INDEX16=A2h ;SMI Enable Register
;****************************************
BIT=07       ;0/1 APMC Write SMI Enable
BIT=06       ;0/1 EXTSMI Signal SMI Enable
BIT=05       ;0/1 Fast Off Timer SMI Enable

;****************************************
INDEX32=A4h ;System Event Enable
;****************************************
BIT=31      ;0/1 Fast Off SMI Enable
BIT=30      ;0/1 INTR Enable
BIT=29      ;0/1 Fast Off NMI Enable
BIT=15      ;0/1 Fast Off IRQ 15 Enable
BIT=14      ;0/1 Fast Off IRQ 14 Enable
BIT=13      ;0/1 Fast Off IRQ 13 Enable
BIT=12      ;0/1 Fast Off IRQ 12 Enable
BIT=11      ;0/1 Fast Off IRQ 11 Enable
BIT=10      ;0/1 Fast Off IRQ 10 Enable
BIT=09      ;0/1 Fast Off IRQ 9 Enable
BIT=08      ;0/1 Fast Off IRQ 8 Enable
BIT=07      ;0/1 Fast Off IRQ 7 Enable
BIT=06      ;0/1 Fast Off IRQ 6 Enable
BIT=05      ;0/1 Fast Off IRQ 5 Enable
BIT=04      ;0/1 Fast Off IRQ 4 Enable
BIT=03      ;0/1 Fast Off IRQ 3 Enable

