;*************** OPTI 386WB: 82C391, 82C392 **********************
;*************** in Datei OPTI391.CFG       **********************
INDEXPORT=22H   ;OPTI-Adressen
DATENPORT=24H
;******************************************************************

INDEX=20H        ; Control-Register 1
;****************************************************************
BIT=76           ; Revision  of 82C391


BIT=3            ;0/1 Single ALE

BIT=2            ;0/1 Extra AT Cycle Waitstate

BIT=1            ;0/1 Emulation Keyboard Reset Control

BIT=0            ;0/1 Fast Reset Enable

INDEX=21H        ; Control Register 2
;****************************************************************

BIT=7            ;0/1 Master Mode Byte Swap Enable

BIT=6            ; Emulation Keyboard Reset Delay Control
                 0=Generate Reset Puls 2ęs later
                 1=Generate reset pulse immediately
BIT=5            ;1/0 Parity Check

BIT=4            ;0/1 Cache

BIT=32           ; Cachesize
                   00= 32KB
                   01= 64KB
                   10= 128KB
                   11= 256KB

BIT=10          ; Cache Write Control
                   00=3T state, write hit cycle
                   01=2T state, early write trailing edge delay
                   10=2T state, no early write
                   11=2T state, early write

INDEX=22H      ; Shadow RAM Control Register I
;****************************************************************

BIT=7          ; ROM Enable at F0000-FFFFF
                  1=Read from ROM/Write to RAM
                  0=Read/write on RAM and RAM is Write-protected

BIT=6          ;0/1 Shadow RAM at D0000h-DFFFFh

BIT=5          ;0/1 Shadow RAM at E0000h-EFFFFh

BIT=4          ;0/1 Shadow RAM at D0000h-DFFFFh Write Prot

BIT=3          ;0/1 Shadow RAM at E0000h-EFFFFh Write Prot

BIT=2          ;1/0 Hidden Refresh

BIT=1          ;0/1 Ignore A20 Gate (undocumented)

BIT=0          ;0/1 Slow Refresh (4 times slower)

Index=23H      ;Shadow RAM Control Register II
;******************************************************************

Bit=7          ;0/1 Shadow RAM at EC00h-EFFFh

Bit=6          ;0/1 Shadow RAM at E800h-EBFFh

Bit=5          ;0/1 Shadow RAM at E400h-E7FFh

Bit=4          ;0/1 Shadow RAM at E000h-E3FFh

Bit=3          ;0/1 Shadow RAM at DC00h-DFFFh

Bit=2          ;0/1 Shadow RAM at D800h-DBFFh

Bit=1          ;0/1 Shadow RAM at D400h-D7FFh

Bit=0          ;0/1 Shadow RAM at D000h-D3FFh

INDEX=24H      ;Index Control Register 1
;******************************************************************

Bit=7654       ;DRAM Typ Bank 0/1
                      0000=B0:256K B1:-
                      0001=B0:256K B1:256K
                      0010=B0:256K B1:1M
                      0011=B0: -   B1: -
                      01xx=B0: -   B1: -
                      1000=B0:1M   B1: -
                      1001=B0:1M   B1:1M
                      1010=B0:1M   B1:4M
               1011=B0:4M   B1:1M
                      1100=B0:4M   B1: -
                      1101=B0:4M   B1:4M
                      111x=B0: -   B1: -

Bit=3                 ;unused
Bit=210               ;DRAM Typ Bank 2/3
                      000=B2:1M   B3:-
                      001=B2:1M   B3:1M
                      010=B2: -   B3: -
                      011=B2:4M   B3:1M
                      100=B2:4M   B3: -
                      101=B2:4M   B3:4M
                      11X=B2: -   B3: -

INDEX=25H      ; DRAM Control Register II
;****************************************************************

BIT=76         ; Read Cycle Wait States
                       00= 2 Waits
                       01= 3 Waits
                       10= 4 Waits
                       11= 5 Waits
BIT=543        ; Write Cycle Wait States
                       000= 2 Waits
                       001= 2 Waits
                       010= 3 Waits
                       011= 3 Waits
                       100= 4 Waits
                       110= 5 Waits
                       101= ???
                       111= ???

BIT=210        ; unused

INDEX=26H      ; Shadow RAM Control Register III
;****************************************************************

BIT=7         ;  unused

BIT=6         ; Shadow RAM Copy enable for address area C0000h-EFFFFh
                0=Read/write at AT-Bus
                1=Read from AT-Bus, Write into  Shadow RAM

BIT=5         ;Shadow Write protect at address area C0000h-CFFFFh
               0=Disabled
               1=Enabled

BIT=4         ;0/1 Shadow RAM at C0000h-CFFFFFh

BIT=3         ;0/1 Shadow RAM at CC000h-CFFFFFh

BIT=2         ;0/1 Shadow RAM at C8000h-CBFFFFh

BIT=1         ;0/1 Shadow RAM at C4000h-C7FFFFh

BIT=0         ;0/1 Shadow RAM at C0000h-C3FFFFh

INDEX=27H     ; Control Register 3
;****************************************************************

BIT=7         ; Cacheable Function
              0=DRAM Cacheable controlled by Bit 3-0
              1=all DRAM are NON-cacheable

BIT=65        ; Unused

BIT=4         ; VIDEO BIOS at C0000h-C8000h area non-cacheable
              0=Cacheable
              1=Non-Cacheable

BIT=3210      ; Cacheable Address-Range
;                   32K-Cache: 8MB,  64K-Cache: 16MB,
;                  128K-Cache:32MB, 256K-Cache: 64MB
              0000=0..64MB
              0001=0.. 4MB
              0010=0.. 8MB
              0011=0..12MB
              0100=0..16MB
              0101=0..20MB
              0110=0..24MB
              0111=0..28MB
              1000=0..32MB
              1001=0..36MB
              1010=0..40MB
              1011=0..44MB
              1100=0..48MB
              1101=0..52MB
              1110=0..56MB
              1111=0..60MB

INDEX=28H  ; Non-Cacheable Block 1 Register I
;****************************************************************

BIT=765    ; Size of Non-cacheable Memory Block 1
            000=64K
            001=128K
            010=256K
            011=512K
            1xx=Disabled
BIT=432    ; Unused

BIT=10     ;Address-Bits of non Cacheable Memory Block 1
           xx=A25..A24

INDEX=29H  ; Non-Cacheable Block 1 Register II
;****************************************************************

BIT=76543210 ; Address-Bits of non Cacheable Memory Block 1
             xxxxxxxx=A23..A16

INDEX=2AH  ; Non-Cacheable Block 2 Register I
;****************************************************************

BIT=765    ; Size of Non-cacheable Memory Block 1
            000=64K
            001=128K
            010=256K
            011=512K
            1xx=Disabled
BIT=432    ; Unused

BIT=10     ;A25..A24 Address-Bits of non Cacheable Memory Block 1

INDEX=2BH  ; Non-Cacheable Block 2 Register II
;****************************************************************

BIT=76543210 ; A23..A16 of non Cacheable Memory Block 1

